Ya, that makes sense. So with 1 row of 8 parallel chips per DIMM, 29 bits would be used to access locations, 0 for chips, and 3 bits for dimm slots. The only thing that confuses me is if for...
Type: Posts; User: John_L
Ya, that makes sense. So with 1 row of 8 parallel chips per DIMM, 29 bits would be used to access locations, 0 for chips, and 3 bits for dimm slots. The only thing that confuses me is if for...
I think i'll take the other approach, extend the address to 34 bits. So when looking at the locations per chip, 8 chips in parallel, and 8 dimm slots total. This 34 bit address needs to be able to...
right, because 2^32 = 4 GB (which is why i was racking my brain). For all 16GB you'd need a 34 bit address than right? So assuming a 4GB system, than i'd reduce the number of DIMM Slots to 2, than...
Thank you, the way you put it made a lot of sense. Since each row represents 4 bytes you'd need a rectangle of 4 (across) by 2^29 (down) to make 2GB. I think the only reason I was struggling was...
I don't have an "assignment", prof, or class. I'm working out of a text book trying to grasp hardware issues, especially memory. Which is probably why i'm not doing so well.
I could scan you the...
Sorry to re-post, but the last thread didn't really help much. Mainly because things weren't explained to me and my goal is to understand. At this point I am looking for the answers, but also...
But it looks like you were estimating transfer rate strictly from main memory, should i estimate the data transfer rate from main memory, and all levels of cache? Than maybe average them out?
...
You kind of lost me there. The only data I have available is the table I gave in my first post. I don't know the width of the bus. With what I have, I must calculate:
a)average effective access...
Sorry for not phrasing properly. My questions are as follows:
1) Is my formula for "average effective access time for memory references" correct? meaning, will it give me a rough estimate?
...
oh ok, so since the number of rows are 4, 4 rows of 8 chips....that means the total number of chips per DIMM slot is 32?
If there is a 3-level cache structure in place with the following characteristics:
organized as column 1) Level, column 2) access time (nano-secs), column 3) Hit %
L1 2nsec...
hold on a sec, you mean 32 rows, isn't 2GB => 2^34 bits. Than 2^34 / 2^29 = 32, so it's 32 rows of 8 chips.....Than is that the total amount of chips I need, 32 * 8...or what's the next step?
I'm kind of lost at this point....further re-reads of the text book hasn't helped and i'm not sure what your trying to indicate to me at this point. Sorry...
2^31 / 2^29 = 4?
so I need 4 chips per DIMM slot?
I'm a bit confused,
2 GB = 2, 147, 483, 648 bytes
2, 147, 483, 648 bytes / 8 DIMM Slots = 268, 435, 456 bytes/Dimm slot
268, 435, 456 bytes / 2^29 locations = 0.5 bytes/location
0.5...
I am new to the hardware realm and am having difficulty with some work i've been assigned from a text book. Any help would be greatly appreciated.
Question:...
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