Simple makefile Problem

[kishorepalle]

Hey Guys,

I am new to unix environment. I am trying to write a make file that compiles C files and then links all the object files into a .a file.

here is my code...

mtc.a : simple.o, simple1.o;
# Compiling source files
simple.o : simple.c
gcc -c simple.c
simple1.o : simple1.c
gcc -c simple1.c
# End of makefile

The file name for this is makeunix. When I type makeunix it displays series of errors like
nwline or ; expected,

simple.o cannot be execute
: No such file or directory
gcc no input files

simple1.o cannot be execute
: No such file or directory
gcc no input files

Even though all the files mtc.a, simple.o, simple.c, simple1.o, simple1.c exist in the same directory.

Anyhelp in this regard is very much appreciated.

Best Regards,
Kishore

[Perspective]

>> mtc.a : simple.o, simple1.o;

lose the comma and semi-colon.

mtc.a: simple.o simple1.o
<tab> <gcc me a .a lib>

[kishorepalle]

Thanks for your reply Perspective...

I changed it to,

mtc.a : simple.o simple1.o
gcc me a .a lib

# Compiling source files
simple.o : simple.c
gcc -c simple.c
simple1.o : simple1.c
gcc -c simple1.c

# End of makefile

It says me a .a lib

gcc: me: No such file or Directory
gcc: a: No such file or Directory
gcc: .a: No such file or Directory

and it still says,
mtc.a: syntax error at line 2: 'Newline or ;' expected.

[itsme86]

I think you have the wrong idea about makefiles. First of all, the 'make' program looks for a few different filenames that contain the build rules. The most commonly used one by far is Makefile. Once the build rules are set up correctly you should just be able to type 'make' and watch it go.

What it looks like you're doing is trying to write a script that compiles the program for you, but the contents of your script look a lot more like a standard Makefile rather than a shell script.

[kishorepalle]

Thanks for the insights on the make itsme86.

Yes youre right...it is just a makefile. And I am writing a makefile script (not shell script )that does the compilation and link the object files together and produce the .a file as it is asked for in the target field.

# start of makefile
#linking in progress

mtc.a : simple.o simple1.o

# Compiling source files
simple.o : simple.c
gcc -c simple.c
simple1.o : simple1.c
gcc -c simple1.c

# End of makefile

When I execute this script, (I think) I am asking it to compile simple.c & simple1.c files and thus produced object files are to be linked to produce one mtc.a file (top of the script).

All it says now is that no object files exist even though they are existing in the folder.

If this is not the way to write this, how can that be done ??? Thanx for your help

[Salem]

Make already knows how to turn C files into object files, so all you really need is this

# A makefile

OBJ = simple1.o simple2.o

foo.a : $(OBJ)
	ar cr $@ $^

Just make sure the ar command is prefixed by a real tab character, and not just a number of spaces.

Save this with the name Makefile
Then just type make at the command prompt

This is what you should see

$ make
cc    -c -o simple1.o simple1.c
cc    -c -o simple1.o simple2.c
ar cr foo.a simple1.o simple2.o