1. ## sequential logic circuits

Hi people,
I am having a tough time understanding sequential logical circuits, and example is here, maybe "flip flops" rings a bell. I just can't understand on my own what's going on with the truth table for it, how are things going in? like it says R=1 and S=0, so what goes on and where does the 2nd input for each NAND gate come from? generally, I don't understand, but the stuff before I do.

http://computer.howstuffworks.com/boolean3.htm

look at the 2nd diagram on the above page, that's what I mean,
John

2. Don't you just love RS NAND flip flops? Try understanding a clocked J/K flip flop.

I believe that the inital state of the second input for each NAND gate is assumed to be 0. The the result from each of the NANDs is queued up for the next NAND.

3. thanks,

it's just hard to understand these things.

4. If i understand correctly your question,
the gate is designed to take one input from the clock
& one input from another transistor. the gate produces a single output which is always the opposite of the other transistor. when current 1 is sent from another transistor , the gate will close
its nod for the clock door(switch open). which makes the
final output 0.