Thread: Linker problem while 'make'-ing

  1. #1
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    Linker problem while 'make'-ing

    The error is:
    Quote Originally Posted by make
    [manasij7479@manasijd cmdline]$ make
    g++ input.cpp -std=c++0x -o input.o -c
    g++ input.o input_test.cpp -std=c++0x -o input_test.o -c
    g++: warning: input.o: linker input file unused because linking not done
    g++ argument.cpp -std=c++0x -o argument.o -c
    g++ argument.o argument_test.cpp -std=c++0x -o argument_test.o -c
    g++: warning: argument.o: linker input file unused because linking not done
    g++ input_test.o argument_test.o test_main.cpp -std=c++0x -o test
    input_test.o: In function `input_test()':
    input_test.cpp: (.text+0x14): undefined reference to `input::input(char**)'
    collect2: ld returned 1 exit status
    make: *** [test] Error 1
    Somehow the linking is not done, and whatever I define isn't available.
    Is there some separate flag necessary for specifying source and object files together ?

  2. #2
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    Quote Originally Posted by manasij7479 View Post
    Is there some separate flag necessary for specifying source and object files together ?
    Not as far as I know. gcc/g++ should be smart enough to figure out a .o is an object file, and doesn't compile it, just links it.

    It would help immensely if you posted your make file, though perhaps you can sort out the make file issues once you see the problem. These two lines (immediately above the red lines) are what's causing the error:
    g++ input.o input_test.cpp -std=c++0x -o input_test.o -c
    ...
    g++ argument.o argument_test.cpp -std=c++0x -o argument_test.o -c
    For some reason you're calling g++ again, this time on the .o file and it's .cpp file, but still using the -c option, so it's strictly compilation, no linking.

  3. #3
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    I misread a bit. I see now that the above use "input.o" and "input_test.cpp". You don't use a .o file if you're strictly compiling. Moving them to the linking line would help:
    g++ input_test.o argument_test.o test_main.cpp -std=c++0x -o test
    You don't have input.o anywhere in that list, so it can't find input::input(char **). You also don't have argument.o in there.

  4. #4
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    For some reason you're calling g++ again, this time on the .o file and it's .cpp file, but still using the -c option, so it's strictly compilation, no linking.
    That is the problem.
    I want to make it somewhat hierarchical, but these object files ... need to be "fused" by force for that.
    It works fine when all the files are given to the compiler at the same time.


    The makefile is.... in a raw form:
    Code:
    test: input_test argument_test test_main.cpp
        g++ input_test.o argument_test.o test_main.cpp -std=c++0x -o test
    
    input_test : input input_test.cpp
        g++ input.o input_test.cpp -std=c++0x -o input_test.o -c
        
    argument_test : argument argument_test.cpp
        g++ argument.o argument_test.cpp -std=c++0x -o argument_test.o -c
    
    input: input.cpp input.h
        g++ input.cpp -std=c++0x -o input.o -c
    
    argument: argument.cpp argument.h
        g++ argument.cpp -std=c++0x -o argument.o -c

  5. #5
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    Quote Originally Posted by anduril462 View Post
    I misread a bit. I see now that the above use "input.o" and "input_test.cpp". You don't use a .o file if you're strictly compiling. Moving them to the linking line would help:

    You don't have input.o anywhere in that list, so it can't find input::input(char **). You also don't have argument.o in there.
    So, in the ultimate line, where I bring the parts together, I give all the object files at the same time ?

  6. #6
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    My basic make file for a single directory with a single target executable looks something like this (change extensions and flags as needed for C++):
    Code:
    CC:= gcc
    CFLAGS :=       -c -Wall
    # Sources are all .c files in this dir
    SRCS :=         $(wildcard *.c)
    # Object files are everything in $SRCS, with the .c replaced by a .o
    OBJS :=         $(patsubst %.c, %.o, $(SRCS))
    TARGET :=       executable_name
    
    # Default target makes the executable, so you just type 'make' at the command line
    default :       $(TARGET)
    
    # Make every .o file require it's corresponding .c file
    # For each such file, call the compiler with the specified flags
    # Use the requisite ($<) as input (the .c file)
    # Use the target name ($@) as the output file name (the .o file)
    %.o : %.c
            $(CC) $(CFLAGS) $< -o $@
    
    # Make the executable require all the object files
    # Use all the requisites ($^), as input files (the .o files) for the linker
    # Output file is $TARGET, which is executable_name
    $(TARGET) :     $(OBJS)
            $(CC) $(LDFLAGS) $^ -o $(TARGET)
    
    # Simple clean up target
    clean :
            rm -f $(OBJS) $(TARGET)

  7. #7
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    Thanks.
    Works nicely.

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