I am in the process of trying to consolidate several IDE project files into one large make file. During the build, the prior projects used a perl file to grab the input source list from the project file to be used to output an automatic C file. That compiler project (TI Code Composer) had a section in it for the source files that looked like this
[Source Files]
Source="..\common\src\file.c"
Source="..\common\src\file2.c"
Source="..\source\file1.c"
Source=".\file2.c"
etc
The perl script can grab all of these files for what it needs to do and everyone is happy
Now for my makefile build, it is a little more cumbersome. I have a section for my object files like this
OBJ = file.o
OBJ += file2.o
OBJ += file1.o
etc
Then I have the rules to make these objects following:
file.o : ..\common\src\file.c
$(CC) $(options) <file>
which gets all of my objects into a list for linking, but doesnt really account for the various source locations. It is desired to keep the output object files in one folder apart from the various source directories.
Is there some cute makefile trick to grab all of the source files and pipe them out to a variable? Something like
echo $(SRC) > sourcefiles.txt
I could just make another section to define all of the source files similar to the OBJ section, but I wanted to keep the number of file sections to a minimum. There will be a lot of "ifeq" sections for various builds and the fewer locations I have to maintain when a new file is added, the better