I am reading GNU Make's manual, here is an example from it:

http://www.cs.utah.edu/dept/old/texi..._toc.html#SEC8

Code:
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)
main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
command.o : command.c defs.h command.h
        cc -c command.c
display.o : display.c defs.h buffer.h
        cc -c display.c
insert.o : insert.c defs.h buffer.h
        cc -c insert.c
search.o : search.c defs.h buffer.h
        cc -c search.c
files.o : files.c defs.h buffer.h command.h
        cc -c files.c
utils.o : utils.c defs.h
        cc -c utils.c
clean :
        rm edit $(objects)
It's interesting that main.o depends on defs.h. I don't think it's necessary to put defs.h for main.o . Because if main.o depends on defs.h, you just need to include <defs.h> in main.c, there is no need to put defs.h as a dependent in a Makefile.

Am I right?