hardware question

Hi,

If SEQ executes 1 instruction per cycle, what is assumed about the memory acess latency?is this a realistic assumption and why?

Thank you

I presume "SEQ" is some processor model.

You can't make that assumption, I think. For example, a 486 can execute many instructions in 1 cycle - but memory reads may take several cycles if it's in external memory. If it's in cache, it's "immediate".

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Mats

The 486 does not implement OOE. Most of its opcodes execute in multiple clock cycles, some of them take only 1. Nothing is immediate. An instruction in cache still requires a memory read cycle to move it into the prefetch queue (the predecessor of the modern instruction pipeline). Only instructions already in the prefetch queue could be considered to execute 'immediately' in the context of the cpu.

http://www.amazon.com/Magazine-Progr...2806929&sr=8-2

Yes, of course, there was a reason I said "immediate" in quotes. By immediate here I mean that there isn't a wait of several cycles in the interface between the processor and the memmory.

And I actually meant that the data needed for the instruction is in cache, and the instruction is "ready for execution in the pipeline". [Actually, thinking more about it, I think only register to register operations are in the set of 1-cycle per instruction in 486].

But certainly a processor that does "one instruction per cycle" will either:
1. Need to "block" (or wait) if the memory can't deliver the data immediately.
2. use memory that is fast enough to deliver data in one clock-cycle.

The second option pretty much eliminates DRAM for anything running faster than a few dozen MHz, since even the fastest models of DRAM designs right now are not able to deliver data in "bad cases" in less than 50 ns. Bad cases here means that "when a refresh is needed" or "when a new page is opened" [pages here has nothing to do with CPU/MMU pages].

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Mats