makefile question

Hi

I have some basic questions about makefile. The makefile I wrote looks like this

Code:

---

CC = g++
target = card.exe

all : $(target)

$(target) : main.o card.o cardItem.o
        $(CC) -Wall main.o card.o cardItem.o -o $(target)

card.o : card.h card.cpp
        $(CC) -c card.cpp card.h
       
cardItem.o : cardItem.cpp cardItem.h
        $(CC) -c cardItem.cpp cardItem.h
       
clean :
        -rm *.o $(target)

---

cardItem.h is linked with card.h ie. inside cardItem.h I have #include "card.h". Does that mean the dependence list of cardItem.o also need to include card.h and card.cpp?

Also do I need to have -Wall for card.o and cardItem.o in order to have the compile check all the code?

Cheers

Remove the .h files from the $(CC) lines.
You don't compile them directly, they're #included by the source.

> Also do I need to have -Wall for card.o and cardItem.o in order to have the compile check all the code?
No, it's too late for -Wall to do it's job when you're combining .o files into an executable.
Add -Wall to the $(CC) lines (along with the -c option).

Investigate the $CFLAGS make variable.