Originally Posted by
Codeplug
>> ...is just a single 32-bit location say, then it would be unnecessary
>> if you are doing single writes and single reads to one 32-bit register, then you can do it without any form of locks
These are dangerous statements without qualification.
Reads and writes to aligned, CPU-sized data, on x86 architectures are atomic operations - in the sense that the execution of the entire read/write operation will not be pre-empted (by a hardware interrupt for instance). This may not be the case on other architectures, alignments, and other-sized data.
That being said, you can still get into trouble due to read/write re-orderings that arise from SMP cache coherency.
If the OP is truly using memory-mapped I/O registers, it may not be an x86 architecture.
gg