Simple GNU Makefile

This is a simple Makefile

Code:

---

CFLAGS = -Wall
CC = gcc

TESTS := $(wildcard encryption/*.c)

tests: $(TESTS)
    echo "TESTS are compiled under tests/"
    echo "TODO: run the testunit"
#    echo $?
$(TESTS):
    echo $@
#    echo $(CC) $(CFLAGS) -DTEST -o tests/$@ [email protected]

---

The problem is it won't run the commands of the target $(TESTS).

What am I missing?

Think about what $(TESTS) expands to. For instance, say you have encryption/a.c and encryption/b.c. Then the rule will expand:

encryption/a.c encryption/b.c:
some commands...

There are no dependencies listed. The files exist. Nothing needs to be done, so make does nothing.

Oh I am so dumb. How could I make such that it replaces each .c by "tests/<filename>" and create a target for it automagically, instead of me having to

Code:

---

encryption/a.c:
    $(CC) ...

---

?

Try something like this:

Code:

---

CFLAGS = -Wall
CC = gcc

TEST_SRCS = $(wildcard encryption/*.c)
TESTS = $(TEST_SRCS:.c=)

.PHONY: tests

tests:
    $(MAKE) CFLAGS="$(CFLAGS) -DTEST" $(TESTS)

---

Thanks a lot.

What should I look for in the manual, in regards to $(TEST_SRCS:.c=)?

Never mind, it is in 4.14 Generating Prerequisites Automatically