I haven't tried your make script but...
First, if I remember correctly, indentation matters in a makefile.
Code:
carClassApp.o: carClassApp.cpp
g++ -c -g carClassApp.cpp
I don't know how much it should be indented but if you use an editor like emacs, you won't have to worry about how many spaces (or one tab) you need for proper indentation.
Also, I bet you'd need to fix:
Code:
g++ Car.o carClassApp.o –g -o car
The output option "-o" should always immediately precede the output file.
Also, the object file targets do have to be explicitly indicated
Code:
Car.o: Car.cpp Car.h
g++ -c -g Car.cpp Car.h -o Car.o
However, if you use automatic variables
Code:
Car.o: Car.cpp Car.h
g++ -c -g $^ -o $@
it becomes simpler. "$^" means replace this with everything in the dependency list and "$@" means replace this with the target.
You can even reduce the entire segment:
Code:
Car.o: Car.cpp Car.h
g++ -c -g Car.cpp Car.h
carClassApp.o: carClassApp.cpp
g++ -c -g carClassApp.cpp
with
Code:
%.o: %.cpp
g++ -c -g $< -o $@
However, for the above to work, you need another target which uses this target as a dependency. So the final version would work like
Code:
SRC = carClass.cpp Car.cpp
OBJ = ${SRC:%.cpp=%.o}
car: $(OBJ)
g++ -o $@ $^
%.o: %.cpp
g++ -c -g $< -o $@