I have a Makefile which is minimal, yet complete. It is the following:
There is a directory called "src" which includes the source files. When I'm running make, I will get a compilation error about having to first create modules before using them. If I do create them manually, then I will be able to use "Make" and it will work then it will work. Is there a way to automatically create them?Code:OUT = example INSTALL_DIR = /usr/local/bin OBJECT = ./obj SOURCE = ./src SRC := $(shell find $(SOURCE) -name *.cc) OBJ := $(SRC:%=$(OBJECT)/%.o) DEPS := $(OBJ:.o=.d) INC_DIRS := $(shell find $(SOURCE) -type d) INC_FLAGS := $(addprefix -I,$(INC_DIRS)) CC = gcc CFLAGS = -pipe -fmodules-ts -std=c++2a DEBUG_FLAGS := $(CFLAGS) -g -Wall -Wextra RELEASE_FLAGS := $(CFLAGS) -O3 -flto debug: $(OBJ) @echo "Building the DEBUG binary..." @$(CC) $(OBJ) -o $(OUT) $(DEBUG_FLAGS) @echo "The binary was built successfully!" release: $(OBJ) @echo "Building the RELEASE binary..." @$(CC) $(OBJ) -o $(OUT) $(RELEASE_FLAGS) @echo "The binary was built successfully!" install: $(OUT) @cp $(OUT) $(INSTALL_DIR) uninstall: @rm $(INSTALL_DIR)/$(OUT) $(OBJECT)/%.cc.o: %.cc @mkdir -p $(dir $@) @echo "Building $@..." @$(CC) $(CFLAGS) -c $< -o $@ .PHONY: clean clean: rm -rf $(OBJECT) $(OUT) -include $(DEPS)