Once tested in C, it gets re-written into a hardware description language (HDL):
Code:
if rising_edge(clk) then
random <= s0 XOR s1 XOR s2;
s0 <= (s0(19 downto 1) & s0(31 downto 19)) XOR (zero(31 downto 13) & s0(18 downto 6));
s1 <= (s1(27 downto 3) & s1(31 downto 25)) XOR (zero(31 downto 7) & s1(29 downto 23));
s2 <= (s2(14 downto 4) & s2(31 downto 11)) XOR (zero(31 downto 21) & s2(28 downto 8));
end if;
So using the preprocessor isn't an improvement, nor is using pointers.
Code:
TMP(s2,0xFFFFFFF0,17, 3,11);
By itself this line is pretty ambiguous, and can't be mapped to hardware.
The rest of my design flow is that the HDL is verified in simulation against the C implementation, then converted to hardware and sort-of-implemented in silicon of an FPGA..
In case you are interested, attached is the resulting logical h/w schematic and a snippet of the FPGA die where the PRNG is placed.
The purple bits is logic resources that makes up the random number generator, the green lines are active wires in this design, and the gray lines are possible connections.