Originally Posted by
hamster_nz
If that is the case we are talking different CPU architectures. That quote if from the RISC-V conditional branches section (BEQ/BNE and so on).
... and it is all CPU/design implementation dependent, and I was just providing a first approximation that is simple to understand, provides a reasonably accurate insight as how branch prediction could work, and is actually used in some CPU designs.
Intel x86 follows the "backward will be taken, forward will not" heuristic/assumption when it first encounters a conditional branch, but my vague understanding is that if it is mis-predicted it gets put in the Branch Target Buffer to help get it right the next time. I haven't looked into it deeply for a long time but am pretty sure that is the case.