Quote:
An acquire barrier is not a yield. It does not in any way signal anything to another thread. All it does it prevent your compiler and hardware from reordering instructions and forces memory consistency. At most this may cause a stall on some architectures until cache changes are visible from other cores.
Yes. That was not the misunderstanding; rather, I had forgotten that loads could down below a load barrier. I was treating it as if it were a barrier to the movement of loads in *both* directions.