Thread: emulate atomic copy and clear volatile give warnings not using it results in clr.w

Code:

typedef volatile union eventTag
...
check.all = event.all;         // a IRQ could happen between
event.all &= ~check.all;       // atomic way to clear it

compiles in to and is safe but compiler complains:
undefined behavior: the order of volatile accesses is undefined in this statement

Code:

 mov.w   &event,&check
 mov.w   &check,R15
 bic.w   R15,&event

if I leave out the volatile and in medium or high optimization

no warnings but if a IRQ sets a event flag between these two lines it will be lost

Code:

 mov.w   &event,&check
 clr.w   &event

is the only solution: Make it a function with pragma no optimization?
As I don't feel turning off and on GIE

update: if I tell it to use a temp register it works with volatile and no warnings

Code:

unsigned int temp = event.all; 
check.all = temp;
event.all &= ~temp;                  // atomic way to clear it


mov.w   &event,R15                   // result is safe atomic-copy-and-clear
mov.w   R15,&check                   // even if a IRQ happens R15 is always restored 
bic.w   R15,&event

I use IAR Workbench
In high optimization it's very good at finding shortcuts in math but in this case I don't want its help.

If I don't use volatile and IAR is trying to be "smart" using clr.w on event, but if a IRQ could just set a new flag it would be lost.
If I use volatile the compiler gives warnings and I don't allow warnings even If know it's OK.
If use volatile and give it a hint how to use a temp register everything is fine.

But what a bug to find if during beta testing everything was done in low optimization
and later switched to high and was not using volatile some events could go missing in thin air.
Though the odds a IRQ happen between those two lines is very small, but you can not program on odds.