Basic Makefile question

[baxy]

Hi,

well the question is how to compile objects in a subdirectory?

./bo/%.o : %.c
	$(CC) $(CFLAGS) <$

the command abouve will compile my objects but leave them in the same directory. However I want them in a different directory. in ./bo directory. How to achieve that ?

EDIT;

I just realize that if i remove ./bo/ from the line it does not work.... why is that ?

thnx

[Nominal Animal]

You need to include the relative path for both sources and targets:

bo/%.o: bo/%.c
	$(CC) $(CFLAGS) $^ -c -o $@

bo/%: bo/%.o
	$(LD) $(LDFLAGS) $^ -o $@

However, it is mode common to put (or copy or generate) a separate Makefile in each directory, and use

directory: directory/Makefile
	cd directory && $(MAKE)

(The directory/Makefile part is only needed or useful if you generate your Makefiles.)

The GNU Make Manual is quite useful, even if some of its features are GNU make specific; most of the features are available in other make variants, too, and the documentation usually mentions if the feature is GNU specific or not.

[baxy]

Thnx i did not know that. Still struggling with c in general but slowly progressing. Truly it is a shock moving from Perl (do as you want policy) to a structured/strict language like c.

[manasij7479]

If you have multiple directories (sooner or later, you will), this can get pretty complicated.
I do it in the following way:
https://github.com/manasij7479/gl/bl...ework/Makefile

You only need to add your folders to the SRCDIRS variable to have everything work nicely.

Recursive make invocation would be more flexible of course, but more trouble to set up.
EDIT: Didn't notice your point on having a build directory.
In that case, having a variable listing the build locations should help.