Code:
main.o: main.c outline.c outline.h ../Jesdisciple/filesystem.h
gcc -ggdb -ansi -c main.c outline.c
You're defeating the purpose of make here. The idea of make is that you only have to compile what needs compiling, as opposed to always compiling both source files.
May I suggest some alternative makefiles that use built-in rules and should perform the same as yours?
Code:
# Makefile
CC = gcc
CFLAGS = -ggdb -ansi
OBJECTS = filesystem.o list.o toolkit.o
filesystem.o: filesystem.c filesystem.h
filesystem.h: list.h
list.o: list.c list.h
list.h: toolkit.h
toolkit.o: toolkit.c toolkit.h
If you want to be really fancy, you can make those dependencies automatically generated.
Code:
# Makefile
CC = gcc
CFLAGS = -ggdb -ansi
OBJECTS = filesystem.o list.o toolkit.o
include depend
.PHONY: depend
depend:
$(CC) -MM $(OBJECTS) > depend
Likewise for the second Makefile, except you'd probably replace the outliner: target with something like this . . . .
Code:
outliner: $(OBJECTS) $(Jesdisciple_OBJECTS)
$(CC) $(CFLAGS) -o $@ $^
Anyway, just thought you might want to know more about what make can do . . . .