Thread: Structure Padding in RISC and CISC

  1. #1
    Registered User
    Join Date
    Jan 2009

    Structure Padding in RISC and CISC


    I would like to know about the Structure Padding in RISC and CISC Processors.

    And would like to know some examples of RISC and CISC Processors......

    Please post your response I am attending the exam ....

    Thanks & Regards
    Karteek Challa

  2. #2
    Registered User
    Join Date
    Dec 2006

  3. #3
    Fountain of knowledge.
    Join Date
    May 2006
    Are you sure you are in the right forum?
    OK maybe you are, but as far as I am aware 'Structure Padding' is not dependant on the type
    of processor, it is dependant on the compiler. Or compiler directives, as the case may be.
    OK maybe that's a bit wrong
    Try reading this

    But basically if different processors do things differently, the compiler needs to know and
    make the adjusments, or maybe you need to tell the compiler with #defines etc....

    I don't see why RISC and CISC should be specified, I mean two different CISC processor might do it differently.

    From Wiki

    Well known RISC families include Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture (including PowerPC), SuperH, and SPARC.

    Examples of CISC processors are the System/360 (excluding the 'scientific' Model 44), VAX, PDP-11, Motorola 68000 family, and Intel x86 architecture based processors.

    Good look with your exam, I failed all mine

  4. #4
    Kernel hacker
    Join Date
    Jul 2007
    Farncombe, Surrey, England
    I agree, RISC and CISC has little to do with structure padding - structure padding has to do with aligning data to match the processors expectations.

    This boils down to:
    1. Correctness - many processor are unable to read and write data at addresses that aren't properly aligned. Some processors have the ability to read/write data that is unaligned. In the ones that don't, a program that tries to write to an unaligned address will cause an excpetion/trap.
    2. Efficency - assuming the processor HAS the ability to read/write unaligned data it will be slower because the processor has to do two steps to combine the input data from two memory reads. If the processor hasn't got the ability in itself to read unaligned addresses, it may still allow these to happen by handling the exception/trap that is caused by the unaligned access. This is MANY times slower than the aligned access - quite possibly 100x slower - and that assumes that it is supported by the OS in the first place.

    Some compilers have the ability to set the alignment wanted for any particular structure or for the whole project. If it is supported, it's generally non-portable, and it is also quite possible to cause code that doesn't actually run correctly on all models of the processor that the compiler targets.

    Compilers can produce warnings - make the compiler programmers happy: Use them!
    Please don't PM me for help - and no, I don't do help over instant messengers.

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