Thread: Structure Padding in RISC and CISC

I agree, RISC and CISC has little to do with structure padding - structure padding has to do with aligning data to match the processors expectations.

This boils down to:
1. Correctness - many processor are unable to read and write data at addresses that aren't properly aligned. Some processors have the ability to read/write data that is unaligned. In the ones that don't, a program that tries to write to an unaligned address will cause an excpetion/trap.
2. Efficency - assuming the processor HAS the ability to read/write unaligned data it will be slower because the processor has to do two steps to combine the input data from two memory reads. If the processor hasn't got the ability in itself to read unaligned addresses, it may still allow these to happen by handling the exception/trap that is caused by the unaligned access. This is MANY times slower than the aligned access - quite possibly 100x slower - and that assumes that it is supported by the OS in the first place.

Some compilers have the ability to set the alignment wanted for any particular structure or for the whole project. If it is supported, it's generally non-portable, and it is also quite possible to cause code that doesn't actually run correctly on all models of the processor that the compiler targets.

--
Mats