Address Offset: 90H
Access Type: Read/Write
Reset Value: 0x0000_0000
Bit [31:00]: IDE0 Task File Data (R/W). This bit field defines the IDE0 Task File Data register. This register
can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written
to this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must
be active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access
32-bit Task File Data, the Byte Enables for all four bytes must be active.
• Bit [31:24]: IDE0 Task File Starting Sector Number (R/W). This bit field defines the IDE0 Task File Starting
Sector Number register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 3 is active.
• Bit [23:16]: IDE0 Task File Sector Count (R/W). This bit field defines the IDE0 Task File Sector Count register.
Access to this bit field is permitted only if the PCI bus Byte Enable for byte 2 is active.
• Bit [15:08]: IDE0 Task File Features (W). This write-only bit field defines the IDE0 Task File Features register.
Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active.
• Bit [15:08]: IDE0 Task File Error (R). This read-only bit field defines the IDE0 Task File Error register. Access
to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active.