typical access time of memory

[Lind]

What is the typical access time of memory in a typical systems today?tens ofcycles?hundreds?thousands? if there is a good web source please tell me so i can read more about it thanks.

[Salem]

The clock rate of the FSB (assuming you're on some kind of recent Intel/AMD technology) would provide some indication.

[CornedBee]

So does your memory latency indicator.

There was a Google tech talk about this stuff recently. But I cannot find it.

[matsp]

Rough guide:
L1 cache 0-2 cycles.
L2 cache 10-20 cycles.
L3 cache 20+ cycles
External memory 50-100 cycles.

This is not set in stone, and it depends on many factors. The above numbers for external memry, by the way, are sort of "good average case", not the worst possible case [which would be that some other device is holding the bus for many hundreds or thousands of cycles].

A single random memory can also cause up to 4 other memory reads because the page-table needs to be accessed. Those are most likely "not best case" memory reads, so you can easily spend 1000 cycles for a single read in this case. Fortunately, for the common case of reading memory in a fairly linear fashion, it only happens once for every 4KB of memory.

If the memory isn't marked present in the page-table you'd also incure a page-fault exception, which causes the processor to go off and execute the page-fault handler. If all it needs to do is mark that page present, you may get away with a few hundred cycles overhead and worst case it needs to read the data in from disk - see you next week [or, let's say a million cycles later or so].

--
Mats

[Lind]

so, typically it's tens of cycles, right?

[matsp]

Yes, a few tens or more.

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Mats