# Thread: I don't get >8 bit computers

1. ## I don't get >8 bit computers

Ok. First take an (ancient) 8 bit computer. To my understanding, and this makes sense, each ram chip has one data pin, for writing and reading, that is connected to an data bus. for the english language we have a bit over 200 common characters to represent, and so computers work with bytes at a time, because 2^8 = 256, and all our characters can be represented by a different pattern with just one byte. However, since memory chips only have one data pin, it wouldn't make sense to store an 8 bit pattern in 8 bits on the same memory chip (you would have to acess it 8 times), and so that one byte gets split across 8 ram chips (a bank) so reading a full 8 bits only takes one pass instead of 8.

A SIMM usually has 8 ram chips, so I understand the computer being able to read 8 bits at a time. But how the hec does it read 16, 32 (and now even 64) at at time? What the doodoo!?

2. I would expect such an array of RAM chips to correspond to different address ranges.

-or-

Do you have a better example?

3. I'll summurise.
a ram chip has one (1) data pin for reading and writing. a typical SIMM has 8 ram chips. when a byte is stored, each bit from that byte gets spread across 8 memory chips.
Q: How does memory be accessed at more than 8 bits at at a time? For example, my 32 bit pc, which has the ability to 'fetch' 32 bits from memory at one time. the key word here is 'one time' or 'at the same time'

from what i've described before the question, it only makes sense to me that computer are able only to acess 8 bits at a time.

4. Are you familiar with such things as address bus and data bus? Even if you are talking about a serial RAM, I would think that more lines apply.

5. Sorry, but...you are wrong and way off.

RAM access is done across the bus and not on just one pin or another. At the very core level the CPU must take the bus, thus taking it from AGP, hard drive, DMA, etc., and use it to access memory. Modern computers fetch 32-bits, but even chips as old as the 8086 and 8088 had 16-bit external buses and 32-bit internal, so it's always been about 32-bit at the core level.

Bits and bytes do not directly come down to pins and pin outs. Bits and bytes have more to do with stored voltage values and are composed of sequences of highs and low(s) voltages represented in the circuit. The data bus is similar to the IDE cable that runs from your drive to the IDE on your board. Only the bus on the board runs much faster. It can get extremely complex and I could never explain it all here but I invite you to look into it via the Intel Technical Reference Manuals for their CPUs, DMAs, APICs, UARTs, etc. They will show you a more complete description of what each pin is for. The diagrams are extremely complex so be forewarned.

How a CPU fetches bytes is not dependent on how many pins a chip has, rather it is dependent on the size of the data pipe from the CPU to the device and vice versa. All modern CPUs fetch 32-bits at a time but it has always been Intel's philosophy that at any one time the programmer should be able to access these 4 bytes at the single byte level.

STOSB - store single byte in AL in ES:(E)DI
STOSW - store single word in AX in ES:(E)DI
STOSD - store single dword in EAX in ES:(E)DI

The next obvious instruction would probably be STOSQ which would store a quad word. I'm not sure if the 64-bit CPUs actually extend the 32-bit explicit return registers or not. It would make sense if they did.

Also don't be fooled by 32-bits. Your FPU actually operates on 80-bits to 128-bits at a time, although you cannot store this many bits at a time in memory.

These bytes also are not fetched in sequential order. Often mobos make use of parallel circuitry so that the bytes are in parallel instead of in line or sequence and all modern Intel CPUs make use of predication, instruction caching, branch prediction, etc. The old CPUs operated in a fetch, decode, execute manner when most modern one's operate on a much more complex system that really limits the fetch portion. The instructions are not fetched in sequence but rather in parallel which makes them extremely fast. There are new technologies every day and there is no way I could explain how all of them work, nor do I know how all of them work. Imagine what happens in a dual CPU setup. Each CPU only processes a portion of the code and yet together they execute the code as if it was executed on a single CPU. Quite nice.

And remember this fetch mechanism is not asking for one voltage per pin, it's pulsing hundreds of thousands/millions of voltages on thousands, even millions of pins per second. The pulsing is controlled by the clock circuit and is timed to the rising and falling edges of the clock cycle.

6. well, you're not quite correct that they always were 16/32 bits.
The 8080 and 8085 were 8 bit internal and external
The 8088 and 80188 were 8 bit external, 16 bit internal.
The 8086 and 80186 were 16 bit internal and external.
80286 may have been 32 bit internally, but I cannot find confirmation of that.

7. Originally Posted by jwenting
80286 may have been 32 bit internally, but I cannot find confirmation of that.
It's 24.

Not the one with Jack Bauer in it. :rolleyes.

8. nice compromise between 16 and 32