Designing State Machine

[axon]

hey guys for the semester project in my computer architecture and logic design course I have to design a processor. I've done quite a bit allready but am stuck at this part: designing a tate machine.

The requirements for the state machine are:

Build a state machine that produces three signals REG, ALU, MEM corresponding to states within the state machine. 

input: W and clk
output: REG, ALU, MEM signals
state table
	W	next state
REG	1	REG
REG	0	ALU
ALU	1	ALU
ALU	0	MEM
MEM	1	MEM
MEM	0	REG

basically, am I supposed to have the next state equal to some binarry number. For example REG = 001, ALU = 010...and so on. Or am I totally off track.

Any suggestions?

BTW: the register, alu, and memory are allready designed.

[Waldo2k2]

you might have more luck getting help for this at megatokyo.com or the OS dev forum on FD

[Salem]

One way is to have a state transition table (fancy name for an array) which contains every input state and the corresponding output state

int state;  // the current state

int state_table[NUM_STATES][NUM_W] = {
    // data
};

Then it's simply

newstate = state_table[state][w];
state = newstate;
return newstate;

[axon]

Thanks salem I'll try that.