sequential logic circuits

This is a discussion on sequential logic circuits within the Tech Board forums, part of the Community Boards category; Hi people, I am having a tough time understanding sequential logical circuits, and example is here, maybe "flip flops" rings ...

  1. #1

    sequential logic circuits

    Hi people,
    I am having a tough time understanding sequential logical circuits, and example is here, maybe "flip flops" rings a bell. I just can't understand on my own what's going on with the truth table for it, how are things going in? like it says R=1 and S=0, so what goes on and where does the 2nd input for each NAND gate come from? generally, I don't understand, but the stuff before I do.

    look at the 2nd diagram on the above page, that's what I mean,

  2. #2
    C++ Developer XSquared's Avatar
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    Jun 2002
    Ontario, Canada
    Don't you just love RS NAND flip flops? Try understanding a clocked J/K flip flop.

    I believe that the inital state of the second input for each NAND gate is assumed to be 0. The the result from each of the NANDs is queued up for the next NAND.
    Last edited by XSquared; 03-09-2003 at 09:46 PM.
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  3. #3

    it's just hard to understand these things.

  4. #4
    Registered User SAMSAM's Avatar
    Join Date
    Nov 2001
    If i understand correctly your question,
    the gate is designed to take one input from the clock
    & one input from another transistor. the gate produces a single output which is always the opposite of the other transistor. when current 1 is sent from another transistor , the gate will close
    its nod for the clock door(switch open). which makes the
    final output 0.

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