Conceptual MIPS related question

Hey guys,

I've been trying to work my head around this problem for ages but I just don't understand what to do.

Given this code:
ADD rd, rs, rt · NAND rd, rs, rt
· LUI rd, imm
· BEQ rs, rt, addr
· LW rd, (rt)
· SW rs, (rt)
· LLI rd, imm
· JALR rd, rs

The earlier parts of the question asked me to the number of bits in the registers, opcode. And I did
Each opcode = 3 bits
Each register =3 bits
Immediete = 8 bits

So this is what I don't get.

If LW and SW use register indirect addressing, how many addresses can this machine index?

I know that register indirect addressing means that the value that needs to be loaded or stored, its address is found in the register rt.
But how can I determine how many addresses this machine needs to index?