MIPS synchronisation (ll/sc)

This is a discussion on MIPS synchronisation (ll/sc) within the Tech Board forums, part of the Community Boards category; I wanted to know that if while using ll/sc there is a change in processor before the sc statement is ...

  1. #1
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    MIPS synchronisation (ll/sc)

    I wanted to know that if while using ll/sc there is a change in processor before the sc statement is executed what would be result.

    E.g.

    CPU 1 ==> $t1 = 1, $t0 = 2
    CPU 2 ==> $t1 = 30, $t0 = 40
    MEMORY ==> $s0 = 99

    If we execute these statements:


    Code:
    ll $t1, 0($s0)     --- CPU 1
    ll $t1, 0($s0)   --- CPU 2
    addi $t1, $t1, 1   --- CPU 2
    sc $t1, 0($s0)   --- CPU 2 ($t1 = 1, $s0 = 100)
    sc $t0, 0($s0)   --- CPU 1
    I know that after the execution (Correct me if I am wrong):

    CPU 2 ==> $t1 = 1, $t0 = 40
    CPU 1 ==> $t1 = 99

    I don't know what will happen to $s0 and $t0 after the CPU 1 command. Will $s0 = 2 ??
    Last edited by stud91; 02-11-2012 at 09:21 AM.

  2. #2
    Registered User Codeplug's Avatar
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    From a random MIPS assembly doc that Google found for me - it says that the source register is set to 0 when SC fails, and 1 when it succeeds.

    So if line 4 succeeds, then $t1 = 1 and $s0 = 100.

    Then line 5 will fail (because $s0 has now been modified since the LL on line 1), so $t0 = 0, and $s0 is still 100 (unless something else has since modified the memory at $s0).

    >> Will $s0 = 2 ??
    No. A failed SC does not modify memory.

    gg

  3. #3
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    Thanks a lot for your reply... I also found that random MIPS assembly doc

    Here it is:
    http://www.weblearn.hs-bremen.de/ris...S/mips-isa.pdf

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