Make all sources in a folder individually

I have one folder (aka. directory) with many .c & .cpp source files in it. They will each become an executable with the same name. As opposed to compiling each individual source file manually, I thought i'd create a makefile to do the trick:

Makefile:

Code:

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# compiles all .c files in a dir 

%.c :
    gcc  -o $*.exe $*.c

---

...of course it doesn't work, but maybe you can see where im trying to go with it...

Is there a simple way to make all sources in a folder individually & automatically?

Check this out.(..the second to the last post).

Bash one liner:

Code:

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for f in *.c; do gcc $f -o `echo $f | sed -e 's/\.c$//'`; done

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I checked out that post manasij... Not exactly what I'm looking for. And thanks MK, but I would like to stick with make if possible.

Specifically, I want to have make iterate through files with an "ex_" prefix and a ".c" suffix within the current directory, compiling each individual source file into a corresponding individual executable file.

So, if a directory lists as:
ex_source.c
ex_source2.c
ex_source3.c
no_ex_source.c
something.else.bat

...then, after running make, it should look like this:

ex_source.c
ex_source.exe
ex_source2.c
ex_source2.exe
ex_source3.c
ex_source3.exe
no_ex_source.c
something.else.bat

...I do NOT want to turn all sources into .o files, then a single exe.

There should be a really concise way to accomplish this without having to edit a makefile every time a random source example is added or removed from the folder, right?? =]

Have you looked at MK27's one-liner?

Quote:

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Originally Posted by laserlight

Have you looked at MK27's one-liner?

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Yes. That is for BASH, not GNU MAKE.

Quote:

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Originally Posted by drum1beta

Yes. That is for BASH, not GNU MAKE.

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Beyond affectation or obsession, it is hard to understand why you would care how a task like this is accomplished. Obviously, it is not for a production grade distribution, it's just for your own convenience.

Make syntax is not, AFAICT, "turing complete", and I would not call it a programming language, or bother trying to do very dynamic things with it. However, this task is a no-brainer using a high level interpreted scripting language. If you don't know any of those, it's still a no-brainer in C or C++ with a system() call or something in it...

Quote:

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Originally Posted by drum1beta

There should be a really concise way to accomplish this without having to edit a makefile every time a random source example is added or removed from the folder, right?? =]

---

Yes, of course there are multiple concise ways to do this, but perhaps "make" is not one of them.

To put it another way: you are saying, "I know that there are hammers, I have in fact used a hammer, so I would like to know how to replace a door handle with a hammer." It might be possible, lol, but who wants to bother? In general, people who've replaced a door handle before will say, "Forget the hammer, use a pair of screwdrivers. MUCH LESS CLUMSY."

I have no particular affinity for bash or make. They serve a niche purpose. You can do this however you want. Since it could obviously be done easily any number of ways, why do you feel it is important to use an awkward or perhaps impossible method?

I'm sorry that you, not only fail to take notice of how much more universal make is in this particular context over bash, but also twist my question around to one completely your own - worthy of its own thread.

I was somewhat general with my first post to this thread, and soon attempted to clarify. Here's more:

* I need/want to use make; im guessing 99% of systems with gnu compiler collection installed also have make. Since gnu make can run inside just about any shell, im not limiting my (or another's) options to just that environment - im actually using somebody else's vista machine right now, and although I know there are several options for installing bash, it's not gonna happen.

* This may end up in a package that doesn't currently depend on bash, but does use make. And yes, it's a fairly popular distribution.

So, until you can prove that this simply can't happen in a Makefile, please back out and leave room for the truth ;]

Personally, I think that your task is more suited to a shell script (or batch file). But if you do want to try and use make for the job, the Functions for File Names and the foreach Function may allow for it.

EDIT:
Bah, after reading more carefully, I think this won't work. Still, maybe it can be a starting point for a working solution.

Thanks laserlight. Even though I had been over those sections of the manual multiple times, you inspired me to give it another go =] this time i meant it [even more]

simple solution (at least to the best of my limited ability) :

Code:

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.PHONY : all

all : $(addsuffix .exe,$(notdir $(basename $(wildcard ex_*.c))))

%.exe : %.c
    gcc -o $@ $< -I.

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...works. My thanks to all of you for the help!!