Greetings.
My name is Rasputin and I'm a makefilic. (Obviously not successful as a comic! )
OK, right to the point (well, maybe not so fast - it needs a build-up):
Consider the following sequence of macros and dependencies, which I wish to refine:
Code:
M4_MODULES = first.m4 second.m4 third.m4 fourth.m4
C_MODULES = first.c second.c third.c fourth.c
O_MODULES = first.o second.o third.o fourth.o
my_program: $(O_MODULES) $(LIBRARIES)
(Yes, lots of steps skipped here; that's not the point of this post.) What's mainly wrong with this is that if I add a fifth module, I have to add fifth.m4, fifth.c, and fifth.o to the respective lines. In a complicated makefile that is error prone. So I came up with the following fix, which does work. (I've tested it.) Note the dot at the end of each module name:
Code:
MODULES = first. second. third. fourth.
M4_MODULES = ${MODULES:.=.m4}
C_MODULES = ${MODULES:.=.c}
O_MODULES = ${MODULES:.=.o}
So if it works, what's my problem? Well, it seems the original module names have their own dependency issues. So it really is necessary to specify:
Code:
MODULES = first second third fourth
without the terminating dots. Thus, I need to substitute for the end of a string, something like:
Code:
M4_MODULES = ${MODULES:$=.m4}
and so on.
The problem is that the above substitution does not work. Neither does $$=.m4 nor does \$=.m4; I'm plumb out of guesses.
SO finally the obvious question:
Does anyone know of an syntax in a makefile macro that will perform end-of-string substitutions?
Thanks much for some assistance with this.
-- Rasputin Paskudniak