Makefile question

[vexed]

I'm pretty confused about makefiles. From what I understand, makefiles can quicken the compilation process by ordering the dependencies in a fashion where the entire program doesn't need to get compiled every time a single of its dependencies is altered.

However, that's as far as my knowledge goes. I know how it basically works but I'm not sure how this concept is implemented in the actual makefile. Could someone please explain the process in laymans terms? I've perused google for information but only find myself more confused.

Thanks!

[Salem]

What are you asking?

How to write a makefile?

Or how make determines the order in which to do things?

GNU Make - GNU Project - Free Software Foundation

[vexed]

Both sort of. In my makefile, if I were to have, for example:

A program that depends on list.o, list1.o and list2.o

list.o depended on list2.o

list1.o also depended on list2.o

Would a correct make file be:

file: list.o list1.o list2.o
gcc list.o list1.o list2.o -o myFile.o

list.o: list.c list2.o
gcc -c list.c list2.o

list1.o: list1.c list2.o
gcc -c list1.c list2.o

list2.o: list2.c
gcc -c list2.c

And if so, would it matter if I had list2.o before list.o and list1.o?

Sorry if what I wrote makes absolutely no sense, I made it up on the spot.

[Salem]

Well each list.o only depends on it's corresponding .c file (and not other .o files).

The first part is OK - the exe depends on all the .o files.

> And if so, would it matter if I had list2.o before list.o and list1.o?
No - make would read the whole file to construct a full set of dependencies.

[vexed]

I'm sorry I don't completely understand. Would it be impossible for one x.o object to depend on another y.o object? What if x.o called a function in y.o?

I have another question as well. As I'm trying to create a makefile, I have a code similar to:

x.o: x.c y.o
gcc -c x.c y.o

And when I call make it says that the rules for x.c cannot be found. Do you have any what my error might be?

[Salem]

The dependency of one .o file to another is resolved at link time (when you produce an exe file).

What you perhaps should have though is
x.o : x.c y.h

Where y.h is the interface to a function in y.c, which x.c uses.

[grumpy]

I'm sorry I don't completely understand. Would it be impossible for one x.o object to depend on another y.o object? What if x.o called a function in y.o?

In "make speak" a dependency between X and Y means that Y must exist before X can be created.

The compiler can, generally, produce x.o by compiling the source. For example, x.c may be compiled by a C compiler to produce x.o. x.o is therefore dependent on x.c

The same goes for y.o.

It is generally not necessary for y.o to exist before x.o can be created, or vice versa.

To create an executable, it is necessary to resolve the linkages between object code that calls a function and corresponding entry point of those functions. If the point where a function is called is in x.o, and the function (as compiled) is in y.o, then the job of the linker is to resolve that.

For that reason, an executable will tend to be dependent on a set of object files and also a set of libraries (which are typically just a special repackaging of object files). The object files, in turn, will be dependent on their corresponding source files.

I have another question as well. As I'm trying to create a makefile, I have a code similar to:

x.o: x.c y.o
gcc -c x.c y.o

And when I call make it says that the rules for x.c cannot be found. Do you have any what my error might be?

Yes, you're mixing up the concepts. The error message is also informing you that x.c does not exist, and make does not know how to create it.

If x.c exists, then the right dependency might be

x.o: x.c y.h
gcc -c x.c

your_executable: x.o y.o
gcc -o your_executable x.o y.o [add other libraries here if needed]

The dependency on y.h might be needed if x.c #include's y.h (although, depending on how the makefile is configured, make might keep track of that automatically)

If x.c is produced as the output of something else (say, by running some program that takes x.dat and produces x.c) then the dependency for x.c, in addition to the above, would be

x.c: x.dat
the_program_that_produces_x.c_from_x.dat x.dat

If x.dat does not exist, then make will complain about not having a rule to create x.dat. If it does exist then, every time x.dat changes, x.c will be recreated from x.dat, then x.o will be created from x.c, and your_executable will be created from x.o and y.o.

[lantzvillian]

Well here is a copy of my basic makefile

 CFLAGS = -g -Wall

CC = gcc
LIBS =  -levent -L/usr/local/lib
INCLUDES = -I/usr/local/include 
SRCS = simpleproxy.c client.c


all: simpleproxy client

# The variable $@ has the value of the target. In this case $@ = psort
simpleproxy: simpleproxy.c
	${CC} ${CFLAGS} ${INCLUDES} simpleproxy.c -o [email protected] ${LIBS}

client: client.c
	${CC} ${CFLAGS} client.c -o [email protected]

depend: 
	makedepend ${SRCS}

clean:
	rm *~ *.txt *.o

# DO NOT DELETE

[vexed]

Thank you for all the replies! They really clarified things for me. You were right, I mistakenly wrote one of the source .c files as a .o and thus the linker simply could not find the .c file. Also, another problem was that I didn't have the development version of one of my libraries. Took me hours to find that one :[.