Makefile to output list of sources

This is a discussion on Makefile to output list of sources within the Tech Board forums, part of the Community Boards category; I am in the process of trying to consolidate several IDE project files into one large make file. During the ...

  1. #1
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    Makefile to output list of sources

    I am in the process of trying to consolidate several IDE project files into one large make file. During the build, the prior projects used a perl file to grab the input source list from the project file to be used to output an automatic C file. That compiler project (TI Code Composer) had a section in it for the source files that looked like this

    [Source Files]
    Source="..\common\src\file.c"
    Source="..\common\src\file2.c"
    Source="..\source\file1.c"
    Source=".\file2.c"


    etc

    The perl script can grab all of these files for what it needs to do and everyone is happy
    Now for my makefile build, it is a little more cumbersome. I have a section for my object files like this

    OBJ = file.o
    OBJ += file2.o
    OBJ += file1.o
    etc

    Then I have the rules to make these objects following:

    file.o : ..\common\src\file.c
    $(CC) $(options) <file>

    which gets all of my objects into a list for linking, but doesnt really account for the various source locations. It is desired to keep the output object files in one folder apart from the various source directories.
    Is there some cute makefile trick to grab all of the source files and pipe them out to a variable? Something like

    echo $(SRC) > sourcefiles.txt

    I could just make another section to define all of the source files similar to the OBJ section, but I wanted to keep the number of file sections to a minimum. There will be a lot of "ifeq" sections for various builds and the fewer locations I have to maintain when a new file is added, the better

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    This is really the wrong forum for Makefile help, as this is strictly for C questions. You either want a site dedicated to Make or our general/tech board. Since it is (I think) a quick answer, you could try something like:

    OBJ = $(filter %.o,$(SRC:.c=.o))

    Which will replace the .c with a .o for every item in your list of sources. It will retain the original path prefix. GNU Make documentation is extensive and has plenty of examples. You can find it on the gnu.org site if you need more info.

    EDIT: I totally misunderstood your question, but you'd be better off defining the source files, and deriving the object files from that. You could use an pattern rules to perform the same basic compilation on all .c files, something like %.o: %.c.
    Last edited by anduril462; 03-01-2011 at 04:07 PM.

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