My mem_n_cpy() in Assembly

This is a discussion on My mem_n_cpy() in Assembly within the Tech Board forums, part of the Community Boards category; Originally Posted by CornedBee Yes, AMD has a superscalar design, too. (Eh, I think that's what superscalar means, anyway.) http://en.wikipedia.org/wiki/Superscalar ...

  1. #16
    Malum in se abachler's Avatar
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    Quote Originally Posted by CornedBee View Post
    Yes, AMD has a superscalar design, too.
    (Eh, I think that's what superscalar means, anyway.)
    http://en.wikipedia.org/wiki/Superscalar

    yes, all modern processors are superscalar, but to greater or lesser degree.

    I cant believe we are still stuck on 64 bit external data buses, we should be up to 512 by now, especially with the large pin count packaging now available.
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    Quote Originally Posted by abachler View Post
    http://en.wikipedia.org/wiki/Superscalar

    yes, all modern processors are superscalar, but to greater or lesser degree.

    I cant believe we are still stuck on 64 bit external data buses, we should be up to 512 by now, especially with the large pin count packaging now available.
    First of all, Athlon64[1] and Pentium4/Core2 processors have 128-bit wide bus. Making the bus wider improves the throughput for sequential access, but unfortunately, a lot of applications are not spending that much time doing sequential access, but rather reading/writing all over the place. With modern CPU's having large caches and clever prefetching, it is actually quite hard to write an application that stalls due to memory throughput - that is, the processor can't fill the 128 bit memory bus today [for sequential access].

    The most likely cause of memory throughput problem is stupid programs that do "memcpy()/memset()" (or similar) operations on large chunks of memory and that doesn't use non-temporal stores - this means that the processor switches from writing to reading to writing to reading for a given piece of memory.

    Edit: [1] The first few models of Athlon64 did not have 128-bit bus, but all 939 socket and newer processors have 128-bit bus.

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    System Novice siavoshkc's Avatar
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    In dual core, 128bit is divided to 2 64bit for each core.
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    Quote Originally Posted by siavoshkc View Post
    In dual core, 128bit is divided to 2 64bit for each core.
    No it's not. The bus is still 128 bit wide, but it is shared via an arbiter to allow both cores to access memory. Any given memory access is EITHER core 0 or core 1, but it's ONE SINGLE bus.

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    System Novice siavoshkc's Avatar
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    No it's not. The bus is still 128 bit wide, but it is shared via an arbiter to allow both cores to access memory. Any given memory access is EITHER core 0 or core 1, but it's ONE SINGLE bus.
    Maybe in new ones its true. But in early AMD dual cores I am sure it was 2x64bit. Then it wasn't true for FX ones.

    [edit]
    This is a thread about it http://www.pcguide.com/vb/showthread.php?t=40148
    Last edited by siavoshkc; 08-26-2008 at 11:55 AM.
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    I don't see where it states that it's using the bus in a shared mode - and I can guarantee that even if it says that, it's incorrect. There are so many things incorrect (speculation/guessing/misunderstandings) in that thread that it makes no sense to even start discussign what is wrong, because there is very little that is right.

    I used to work for AMD, so I have seen the internal documentation and the specs for processors before they came to real users.

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