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I might write it as:

void print_it(const vector<string>& details)
because the vector<string> comes with size information, but has nothing to do with system verilog. Then there are other, more...

Yes, some things are similiar, but the language is sufficiently different that, as a C++ programmer with no prior knowledge of system verilog, I cannot help you beyond telling you that you are...

*Thread moved to Tech board*

So, what is your C++ code? If you really mean to say that you are programming in Verilog instead, then this is not the right place to be asking this question.