brace-enclosed error

Hi i am trying to compile this code

Code:

const HwrM68328Type kInitial68328RegisterValues = { 0x0C, // Byte scr; // $000: System Control Register { 0 }, // Byte ___filler0[0x004-0x001]; // The following ID stuff is not present on earlier chips (before ??) hwr328chipID328, // Byte chipID; // $004: Chip ID Register hwr328maskID1H58B, // Byte maskID; // $005: Mask ID Register 0x00, // Word swID; // $006: Software ID Register { 0 }, // Byte ___filler1[0x100-0x008]; 0x0000, // Word csAGroupBase; // $100: Chip Select Group A Base Register 0x0000, // Word csBGroupBase; // $102: Chip Select Group B Base Register 0x0000, // Word csCGroupBase; // $104: Chip Select Group C Base Register 0x0000, // Word csDGroupBase; // $106: Chip Select Group D Base Register 0x0000, // Word csAGroupMask; // $108: Chip Select Group A Mask Register 0x0000, // Word csBGroupMask; // $10A: Chip Select Group B Mask Register 0x0000, // Word csCGroupMask; // $10C: Chip Select Group C Mask Register 0x0000, // Word csDGroupMask; // $10E: Chip Select Group D Mask Register 0x00010006, // DWord csASelect0; // $110: Group A Chip Select 0 Register 0x00010006, // DWord csASelect1; // $114: Group A Chip Select 1 Register 0x00010006, // DWord csASelect2; // $118: Group A Chip Select 2 Register 0x00010006, // DWord csASelect3; // $11C: Group A Chip Select 3 Register 0x00000000, // DWord csBSelect0; // $120: Group B Chip Select 0 Register 0x00000000, // DWord csBSelect1; // $124: Group B Chip Select 1 Register 0x00000000, // DWord csBSelect2; // $128: Group B Chip Select 2 Register 0x00000000, // DWord csBSelect3; // $12C: Group B Chip Select 3 Register 0x00010006, // DWord csCSelect0; // $130: Group C Chip Select 0 Register 0x00010006, // DWord csCSelect1; // $134: Group C Chip Select 1 Register 0x00010006, // DWord csCSelect2; // $138: Group C Chip Select 2 Register 0x00010006, // DWord csCSelect3; // $13C: Group C Chip Select 3 Register 0x00000000, // DWord csDSelect0; // $140: Group D Chip Select 0 Register 0x00000000, // DWord csDSelect1; // $144: Group D Chip Select 1 Register 0x00000000, // DWord csDSelect2; // $148: Group D Chip Select 2 Register 0x00000000, // DWord csDSelect3; // $14C: Group D Chip Select 3 Register 0x0000, // Word csDebug; // $150: Chip Select debug register { 0 }, // Byte ___filler2[0x200-0x152]; 0x2400, // Word pllControl; // $200: PLL Control Register 0x0123, // Word pllFreqSel; // $202: PLL Frequency Select Register 0x0000, // Word pllTest; // $204: PLL Test Register { 0 }, // Byte __filler44; 0x1F, // Byte pwrControl; // $207: Power Control Register { 0 }, // Byte ___filler3[0x300-0x208]; 0x00, // Byte intVector; // $300: Interrupt Vector Register { 0 }, // Byte ___filler4; 0x0000, // Word intControl; // $302: Interrupt Control Register 0x00FF, // Word intMaskHi; // $304: Interrupt Mask Register/HIGH word 0xFFFF, // Word intMaskLo; // $306: Interrupt Mask Register/LOW word 0x00FF, // Word intWakeupEnHi; // $308: Interrupt Wakeup Enable Register 0xFFFF, // Word intWakeupEnLo; // $30A: Interrupt Wakeup Enable Register 0x0000, // Word intStatusHi; // $30C: Interrupt Status Register/HIGH word 0x0000, // Word intStatusLo; // $30E: Interrupt Status Register/LOW word 0x0000, // Word intPendingHi; // $310: Interrupt Pending Register 0x0000, // Word intPendingLo; // $312: Interrupt Pending Register { 0 }, // Byte ___filler4a[0x400-0x314]; 0x00, // Byte portADir; // $400: Port A Direction Register 0x00, // Byte portAData; // $401: Port A Data Register { 0 }, // Byte ___filler5; 0x00, // Byte portASelect; // $403: Port A Select Register { 0 }, // Byte ___filler6[4]; 0x00, // Byte portBDir; // $408: Port B Direction Register 0x00, // Byte portBData; // $409: Port B Data Register { 0 }, // Byte ___filler7; 0x00, // Byte portBSelect; // $40B: Port B Select Register { 0 }, // Byte ___filler8[4]; 0x00, // Byte portCDir; // $410: Port C Direction Register 0x00, // Byte portCData; // $411: Port C Data Register { 0 }, // Byte ___filler9; 0x00, // Byte portCSelect; // $413: Port C Select Register { 0 }, // Byte ___filler10[4]; 0x00, // Byte portDDir; // $418: Port D Direction Register 0x00, // Byte portDData; // $419: Port D Data Register 0xFF, // Byte portDPullupEn; // $41A: Port D Pull-up Enable { 0 }, // Byte ___filler11; 0x00, // Byte portDPolarity; // $41C: Port D Polarity Register 0x00, // Byte portDIntReqEn; // $41D: Port D Interrupt Request Enable { 0 }, // Byte ___filler12; 0x00, // Byte portDIntEdge; // $41F: Port D IRQ Edge Register 0x00, // Byte portEDir; // $420: Port E Direction Register 0x00, // Byte portEData; // $421: Port E Data Register 0x80, // Byte portEPullupEn; // $422: Port E Pull-up Enable 0x80, // Byte portESelect; // $423: Port E Select Register { 0 }, // Byte ___filler14[4]; 0x00, // Byte portFDir; // $428: Port F Direction Register 0x00, // Byte portFData; // $429: Port F Data Register 0xFF, // Byte portFPullupEn; // $42A: Port F Pull-up Enable 0xFF, // Byte portFSelect; // $42B: Port F Select Register { 0 }, // Byte ___filler16[4]; 0x00, // Byte portGDir; // $430: Port G Direction Register 0x00, // Byte portGData; // $431: Port G Data Register 0xFF, // Byte portGPullupEn; // $432: Port G Pull-up Enable 0xFF, // Byte portGSelect; // $433: Port G Select Register { 0 }, // Byte ___filler18[4]; 0x00, // Byte portJDir; // $438: Port J Direction Register 0x00, // Byte portJData; // $439: Port J Data Register { 0 }, // Byte ___filler19; 0x00, // Byte portJSelect; // $43B: Port J Select Register { 0 }, // Byte ___filler19a[4]; 0x00, // Byte portKDir; // $440: Port K Direction Register 0x00, // Byte portKData; // $441: Port K Data Register 0x3F, // Byte portKPullupEn; // $442: Port K Pull-up Enable 0x3F, // Byte portKSelect; // $443: Port K Select Register { 0 }, // Byte ___filler21[4]; 0x00, // Byte portMDir; // $448: Port M Direction Register 0x00, // Byte portMData; // $449: Port M Data Register 0xFF, // Byte portMPullupEn; // $44A: Port M Pull-up Enable Register 0x02, // Byte portMSelect; // $44B: Port M Select Register { 0 }, // Byte ___filler22[4]; { 0 }, // Byte ___filler23[0x500-0x450]; 0x0000, // Word pwmControl; // $500: PWM Control Register 0x0000, // Word pwmPeriod; // $502: PWM Period Register 0x0000, // Word pwmWidth; // $504: PWM Width Register 0x0000, // Word pwmCounter; // $506: PWM Counter { 0 }, // Byte ___filler24[0x600-0x508]; 0x0000, // Word tmr1Control; // $600: Timer 1 Control Register 0x0000, // Word tmr1Prescaler; // $602: Timer 1 Prescaler Register 0xFFFF, // Word tmr1Compare; // $604: Timer 1 Compare Register 0x0000, // Word tmr1Capture; // $606: Timer 1 Capture Register 0x0000, // Word tmr1Counter; // $608: Timer 1 Counter Register 0x0000, // Word tmr1Status; // $60A: Timer 1 Status Register 0x0000, // Word tmr2Control; // $60C: Timer 2 Control Register 0x0000, // Word tmr2Prescaler; // $60E: Timer 2 Prescaler Register 0xFFFF, // Word tmr2Compare; // $610: Timer 2 Compare Register 0x0000, // Word tmr2Capture; // $612: Timer 2 Capture Register 0x0000, // Word tmr2Counter; // $614: Timer 2 Counter Register 0x0000, // Word tmr2Status; // $616: Timer 2 Status Register 0x0000, // Word wdControl; // $618: Watchdog Control Register 0x0000, // Word wdReference; // $61A: Watchdog Reference Register 0x0000, // Word wdCounter; // $61C: Watchdog Counter { 0 }, // Byte ___filler25[0x700-0x61E]; 0x0000, // Word spiSlave; // $700: SPI Slave Register { 0 }, // Byte ___filler26[0x800-0x702]; 0x0000, // Word spiMasterData; // $800: SPI Master Data Register 0x0000, // Word spiMasterControl; // $802: SPI Master Control Register { 0 }, // Byte ___filler27[0x900-0x804]; 0x0000, // Word uControl; // $900: Uart Control Register 0x003F, // Word uBaud; // $902: Uart Baud Control Register 0x0000, // Word uReceive; // $904: Uart Receive Register 0x0000, // Word uTransmit; // $906: Uart Transmit Register 0x0000, // Word uMisc; // $908: Uart Miscellaneous Register { 0 }, // Byte ___filler28[0xA00-0x90A]; 0x00000000, // DWord lcdStartAddr; // $A00: Screen Starting Address Register { 0 }, // Byte ___filler29; 0xFF, // Byte lcdPageWidth; // $A05: Virtual Page Width Register { 0 }, // Byte ___filler30[2]; 0x03FF, // Word lcdScreenWidth; // $A08: Screen Width Register 0x01FF, // Word lcdScreenHeight; // $A0A: Screen Height Register { 0 }, // Byte ___filler31[0xA18-0xA0C]; 0x0000, // Word lcdCursorXPos; // $A18: Cursor X Position 0x0000, // Word lcdCursorYPos; // $A1A: Cursor Y Position 0x0101, // Word lcdCursorWidthHeight; // $A1C: Cursor Width and Height { 0 }, // Byte ___filler32; 0x7F, // Byte lcdBlinkControl; // $A1F: Blink Control Register 0x00, // Byte lcdPanelControl; // $A20: Panel Interface Control Register 0x00, // Byte lcdPolarity; // $A21: Polarity Config Register 0x00, // Byte ___filler33; 0x00, // Byte lcdACDRate; // $A23: ACD (M) Rate Control Register 0x00, // Byte ___filler34; 0x00, // Byte lcdPixelClock; // $A25: Pixel Clock Divider Register 0x00, // Byte ___filler35; 0x40, // Byte lcdClockControl; // $A27: Clocking Control Register 0x00, // Byte ___filler36; 0x3E, // Byte lcdLastBufferAddr; // $A29: Last Buffer Address Register 0x00, // Byte ___filler37; 0x3F, // Byte lcdOctetTermCount; // $A2B: Octet Terminal Count Register 0x00, // Byte ___filler38; 0x00, // Byte lcdPanningOffset; // $A2D: Panning Offset Register { 0 }, // Byte ___filler39[3]; 0xB9, // Byte lcdFrameRate; // $A31: Frame Rate Control Modulation Register 0x1073, // Word lcdGrayPalette; // $A32: Gray Palette Mapping Register 0x00, // Byte lcdReserved; // $A34: Reserved { 0 }, // Byte ___filler40[0xB00-0xA35]; 0x00000000, // DWord rtcHourMinSec; // $B00: RTC Hours, Minutes, Seconds Register 0x00000000, // DWord rtcAlarm; // $B04: RTC Alarm Register 0x00000000, // DWord rtcReserved; // $B08: RTC Reserved 0x0000, // Word rtcControl; // $B0C: RTC Control Register 0x0000, // Word rtcIntStatus; // $B0E: RTC Interrupt Status Register 0x0000, // Word rtcIntEnable; // $B10: RTC Interrupt Enable Register 0x0000 // Word stopWatch; // $B12: Stopwatch Minutes }; //line 321

and i get this error:

Code:

./../SrcShared/Hardware/EmRegs328.cpp:321: error: brace-enclosed initializer used to initialize `UInt8'

I checked google and it probably is a bug of th gcc 3.4.6. I tried changing it in many ways but i still get the same error or simalar.
I checked
http://en.wikipedia.org/wiki/Const

Is it correct to declare const like this?

Code:

const HwrM68328Type kInitial68328RegisterValues = { 0x0C, { 0 }, ... 0x0000 };

should there a semicolon at 0x0000, in the last part. are the braces correct?

It seems that there shouldn't be braces around 0-s.

no offence, but it is more likely a bug in your code than a bug in gcc.

can you post the definition of HwrM68328Type?

it's most likely that your initialiser doesn't match the structure of HwrM68328Type exactly.

Quote:

Originally Posted by anon

It seems that there shouldn't be braces around 0-s.

nope that's fine if he has structs within structs

Code:

struct A { int x; }; struct B { int y; }; struct C { short v1; int v2; A v3; double v4; B v5; }; const C cVal = { 1, 2, { 0 }, 1.2, { 0 } };

compiles fine.

It looks like you've several array initializers that aren't arrays, and thus shouldn't be enclosed in braces. For example __filler44, ___filler4, ___filler5, ___filler7, ___filler9, ___filler11, ___filler12, ___filler19, ___filler29 and ___filler32.

Code:

{ 0 }, // Byte __filler44; . . { 0 }, // Byte ___filler4; . . { 0 }, // Byte ___filler5; . . { 0 }, // Byte ___filler7; . . { 0 }, // Byte ___filler9; . . { 0 }, // Byte ___filler11; . . { 0 }, // Byte ___filler12; . . { 0 }, // Byte ___filler19; . . { 0 }, // Byte ___filler29; . . { 0 }, // Byte ___filler32;

This is the struct of HwrM68328Type

Code:

struct HwrM68328Type { UInt8 scr; // $000: System Control Register UInt8 ___filler0[0x004-0x001]; // The following ID stuff is not present on earlier chips (before ??) UInt8 chipID; // $004: Chip ID Register UInt8 maskID; // $005: Mask ID Register UInt16 swID; // $006: Software ID Register UInt8 ___filler1[0x100-0x008]; UInt16 csAGroupBase; // $100: Chip Select Group A Base Register UInt16 csBGroupBase; // $102: Chip Select Group B Base Register UInt16 csCGroupBase; // $104: Chip Select Group C Base Register UInt16 csDGroupBase; // $106: Chip Select Group D Base Register UInt16 csAGroupMask; // $108: Chip Select Group A Mask Register UInt16 csBGroupMask; // $10A: Chip Select Group B Mask Register UInt16 csCGroupMask; // $10C: Chip Select Group C Mask Register UInt16 csDGroupMask; // $10E: Chip Select Group D Mask Register UInt32 csASelect0; // $110: Group A Chip Select 0 Register UInt32 csASelect1; // $114: Group A Chip Select 1 Register UInt32 csASelect2; // $118: Group A Chip Select 2 Register UInt32 csASelect3; // $11C: Group A Chip Select 3 Register UInt32 csBSelect0; // $120: Group B Chip Select 0 Register UInt32 csBSelect1; // $124: Group B Chip Select 1 Register UInt32 csBSelect2; // $128: Group B Chip Select 2 Register UInt32 csBSelect3; // $12C: Group B Chip Select 3 Register UInt32 csCSelect0; // $130: Group C Chip Select 0 Register UInt32 csCSelect1; // $134: Group C Chip Select 1 Register UInt32 csCSelect2; // $138: Group C Chip Select 2 Register UInt32 csCSelect3; // $13C: Group C Chip Select 3 Register UInt32 csDSelect0; // $140: Group D Chip Select 0 Register UInt32 csDSelect1; // $144: Group D Chip Select 1 Register UInt32 csDSelect2; // $148: Group D Chip Select 2 Register UInt32 csDSelect3; // $14C: Group D Chip Select 3 Register UInt16 csDebug; // $150: Chip Select debug register UInt8 ___filler2[0x200-0x152]; UInt16 pllControl; // $200: PLL Control Register UInt16 pllFreqSel; // $202: PLL Frequency Select Register UInt16 pllTest; // $204: PLL Test Register UInt8 __filler44; UInt8 pwrControl; // $207: Power Control Register UInt8 ___filler3[0x300-0x208]; UInt8 intVector; // $300: Interrupt Vector Register UInt8 ___filler4; UInt16 intControl; // $302: Interrupt Control Register UInt16 intMaskHi; // $304: Interrupt Mask Register/HIGH word UInt16 intMaskLo; // $306: Interrupt Mask Register/LOW word UInt16 intWakeupEnHi; // $308: Interrupt Wakeup Enable Register UInt16 intWakeupEnLo; // $30A: Interrupt Wakeup Enable Register UInt16 intStatusHi; // $30C: Interrupt Status Register/HIGH word UInt16 intStatusLo; // $30E: Interrupt Status Register/LOW word UInt16 intPendingHi; // $310: Interrupt Pending Register UInt16 intPendingLo; // $312: Interrupt Pending Register UInt8 ___filler4a[0x400-0x314]; UInt8 portADir; // $400: Port A Direction Register UInt8 portAData; // $401: Port A Data Register UInt8 ___filler5; UInt8 portASelect; // $403: Port A Select Register UInt8 ___filler6[4]; UInt8 portBDir; // $408: Port B Direction Register UInt8 portBData; // $409: Port B Data Register UInt8 ___filler7; UInt8 portBSelect; // $40B: Port B Select Register UInt8 ___filler8[4]; UInt8 portCDir; // $410: Port C Direction Register UInt8 portCData; // $411: Port C Data Register UInt8 ___filler9; UInt8 portCSelect; // $413: Port C Select Register UInt8 ___filler10[4]; UInt8 portDDir; // $418: Port D Direction Register UInt8 portDData; // $419: Port D Data Register UInt8 portDPullupEn; // $41A: Port D Pull-up Enable UInt8 ___filler11; UInt8 portDPolarity; // $41C: Port D Polarity Register UInt8 portDIntReqEn; // $41D: Port D Interrupt Request Enable UInt8 ___filler12; UInt8 portDIntEdge; // $41F: Port D IRQ Edge Register UInt8 portEDir; // $420: Port E Direction Register UInt8 portEData; // $421: Port E Data Register UInt8 portEPullupEn; // $422: Port E Pull-up Enable UInt8 portESelect; // $423: Port E Select Register UInt8 ___filler14[4]; UInt8 portFDir; // $428: Port F Direction Register UInt8 portFData; // $429: Port F Data Register UInt8 portFPullupEn; // $42A: Port F Pull-up Enable UInt8 portFSelect; // $42B: Port F Select Register UInt8 ___filler16[4]; UInt8 portGDir; // $430: Port G Direction Register UInt8 portGData; // $431: Port G Data Register UInt8 portGPullupEn; // $432: Port G Pull-up Enable UInt8 portGSelect; // $433: Port G Select Register UInt8 ___filler18[4]; UInt8 portJDir; // $438: Port J Direction Register UInt8 portJData; // $439: Port J Data Register UInt8 ___filler19; UInt8 portJSelect; // $43B: Port J Select Register UInt8 ___filler19a[4]; UInt8 portKDir; // $440: Port K Direction Register UInt8 portKData; // $441: Port K Data Register UInt8 portKPullupEn; // $442: Port K Pull-up Enable UInt8 portKSelect; // $443: Port K Select Register UInt8 ___filler21[4]; UInt8 portMDir; // $448: Port M Direction Register UInt8 portMData; // $449: Port M Data Register UInt8 portMPullupEn; // $44A: Port M Pull-up Enable Register UInt8 portMSelect; // $44B: Port M Select Register UInt8 ___filler22[4]; UInt8 ___filler23[0x500-0x450]; UInt16 pwmControl; // $500: PWM Control Register UInt16 pwmPeriod; // $502: PWM Period Register UInt16 pwmWidth; // $504: PWM Width Register UInt16 pwmCounter; // $506: PWM Counter UInt8 ___filler24[0x600-0x508]; UInt16 tmr1Control; // $600: Timer 1 Control Register UInt16 tmr1Prescaler; // $602: Timer 1 Prescaler Register UInt16 tmr1Compare; // $604: Timer 1 Compare Register UInt16 tmr1Capture; // $606: Timer 1 Capture Register UInt16 tmr1Counter; // $608: Timer 1 Counter Register UInt16 tmr1Status; // $60A: Timer 1 Status Register UInt16 tmr2Control; // $60C: Timer 2 Control Register UInt16 tmr2Prescaler; // $60E: Timer 2 Prescaler Register UInt16 tmr2Compare; // $610: Timer 2 Compare Register UInt16 tmr2Capture; // $612: Timer 2 Capture Register UInt16 tmr2Counter; // $614: Timer 2 Counter Register UInt16 tmr2Status; // $616: Timer 2 Status Register UInt16 wdControl; // $618: Watchdog Control Register UInt16 wdReference; // $61A: Watchdog Reference Register UInt16 wdCounter; // $61C: Watchdog Counter UInt8 ___filler25[0x700-0x61E]; UInt16 spiSlave; // $700: SPI Slave Register UInt8 ___filler26[0x800-0x702]; UInt16 spiMasterData; // $800: SPI Master Data Register UInt16 spiMasterControl; // $802: SPI Master Control Register UInt8 ___filler27[0x900-0x804]; UInt16 uControl; // $900: Uart Control Register UInt16 uBaud; // $902: Uart Baud Control Register UInt16 uReceive; // $904: Uart Receive Register UInt16 uTransmit; // $906: Uart Transmit Register UInt16 uMisc; // $908: Uart Miscellaneous Register UInt8 ___filler28[0xA00-0x90A]; UInt32 lcdStartAddr; // $A00: Screen Starting Address Register UInt8 ___filler29; UInt8 lcdPageWidth; // $A05: Virtual Page Width Register UInt8 ___filler30[2]; UInt16 lcdScreenWidth; // $A08: Screen Width Register UInt16 lcdScreenHeight; // $A0A: Screen Height Register UInt8 ___filler31[0xA18-0xA0C]; UInt16 lcdCursorXPos; // $A18: Cursor X Position UInt16 lcdCursorYPos; // $A1A: Cursor Y Position UInt16 lcdCursorWidthHeight; // $A1C: Cursor Width and Height UInt8 ___filler32; UInt8 lcdBlinkControl; // $A1F: Blink Control Register UInt8 lcdPanelControl; // $A20: Panel Interface Control Register UInt8 lcdPolarity; // $A21: Polarity Config Register UInt8 ___filler33; UInt8 lcdACDRate; // $A23: ACD (M) Rate Control Register UInt8 ___filler34; UInt8 lcdPixelClock; // $A25: Pixel Clock Divider Register UInt8 ___filler35; UInt8 lcdClockControl; // $A27: Clocking Control Register UInt8 ___filler36; UInt8 lcdLastBufferAddr; // $A29: Last Buffer Address Register UInt8 ___filler37; UInt8 lcdOctetTermCount; // $A2B: Octet Terminal Count Register UInt8 ___filler38; UInt8 lcdPanningOffset; // $A2D: Panning Offset Register UInt8 ___filler39[3]; UInt8 lcdFrameRate; // $A31: Frame Rate Control Modulation Register UInt16 lcdGrayPalette; // $A32: Gray Palette Mapping Register UInt8 lcdReserved; // $A34: Reserved UInt8 ___filler40[0xB00-0xA35]; UInt32 rtcHourMinSec; // $B00: RTC Hours, Minutes, Seconds Register UInt32 rtcAlarm; // $B04: RTC Alarm Register UInt32 rtcReserved; // $B08: RTC Reserved UInt16 rtcControl; // $B0C: RTC Control Register UInt16 rtcIntStatus; // $B0E: RTC Interrupt Status Register UInt16 rtcIntEnable; // $B10: RTC Interrupt Enable Register UInt16 stopWatch; // $B12: Stopwatch Minutes };

Since there are no structs within structs, then the question is answered?

Quote:

Originally Posted by anon

Since there are no structs within structs, then the question is answered?

looks like you were right. jdc, remove the braces around the 0's and see if that works.

Hm. Looks like another difference between C and C++. Anyone with C&V? [Feeling lazy.]

Quote:

Originally Posted by ChaosEngine

looks like you were right. jdc, remove the braces around the 0's and see if that works.

No, actually there are some arrays, just not as many as they thought. ;)

Quote:

Originally Posted by Dave_Sinkula

Hm. Looks like another difference between C and C++. Anyone with C&V? [Feeling lazy.]

No difference in this case.

Quote:

Originally Posted by swoopy

No difference in this case.

This is valid C:

Code:

int answer = {42};

Yet this is valid C but not valid C++:

Code:

#include <stdio.h> struct example { int a; }; int main(void) { struct example answer = { {42}, }; printf("%d\n", answer.a); return 0; }

At least from a mere compiler test -- it may me a bug (but I tend not to say that without further investigation).

Dave, that has nothing to do with the code posted.

Sure it does. Run it through a C compiler [edit]gcc[/edit]. Same issue, smaller form.

>Sure it does. Run it through a C compiler. Same issue, smaller form.
I'm not disagreeing. But did you see my first post? And my second post?

Please Quzah or Salem, give me a hand here.

Of course this is a C++ forum. But C++ incorporates C90 at least to a degree.

Here we see that,

Quote:

The initializer for a scalar shall be a single expression, optionally enclosed in braces.

Yet this would not appear to be what is occurring, and it does appear to be language dependent.

Yes, you've pinpointed the issue in C++. My question was in regard to a reference to where exactly the difference might be highlighted in a C++ reference.

You'd think after they posted the struct definition, the initialization would become obvious.

>The initializer for a scalar shall be a single expression, optionally enclosed in braces.
Well, I didn't think an array was a scalar.

Quote:

Originally Posted by swoopy

>The initializer for a scalar shall be a single expression, optionally enclosed in braces.
Well, I didn't think an array was a scalar.

Uh. It isn't.

Quote:

Originally Posted by swoopy

It looks like you've several array initializers that aren't arrays, and thus shouldn't be enclosed in braces. For example __filler44, ___filler4, ___filler5, ___filler7, ___filler9, ___filler11, ___filler12, ___filler19, ___filler29 and ___filler32.

Code:

{ 0 }, // Byte __filler44; . . { 0 }, // Byte ___filler4; . . { 0 }, // Byte ___filler5; . . { 0 }, // Byte ___filler7; . . { 0 }, // Byte ___filler9; . . { 0 }, // Byte ___filler11; . . { 0 }, // Byte ___filler12; . . { 0 }, // Byte ___filler19; . . { 0 }, // Byte ___filler29; . . { 0 }, // Byte ___filler32;

But "[y]ou'd think after they posted the struct definition" this was obvious.

But if I get what you're saying, this should compile either way. So maybe he's using:

Code:

gcc EmRegs328.cpp

When he should be using:

Code:

g++ EmRegs328.cpp

Quote:

Originally Posted by swoopy

But if I get what you're saying, this should compile either way. So maybe he's using:

Code:

gcc EmRegs328.cpp

When he should be using:

Code:

g++ EmRegs328.cpp

No, I'm asking the reverse, in a way.

S/He's compiling C++ as C++. I'm asking about the difference with C instead of C++.

But my feeling is if you're going to use brackets, use them for all scalars, which is not the case here. But perhaps the inconsistency does not bother you.

>S/He's compiling C++ as C++.
I don't think so. Because if that was the case, then according to you, it would have compiled. Or maybe I'm missing something.

Please stay on the topic you're tying a grill my butt for. This is not about consistency, it's about correctness.

Quote:

Originally Posted by swoopy

>S/He's compiling C++ as C++.
I don't think so. Because if that was the case, then according to you, it would have compiled. Or maybe I'm missing something.

No. It compiles in C, but not in C++.

Here's my interpretation of your take. The braces are optional in C++. Thus the original code should have compiled. Correct?

Quote:

Originally Posted by swoopy

Here's my interpretation of your take. The braces are optional in C++. Thus the original code should have compiled. Correct?

Backwards.

The code should have compiled in C. It doesn't in C++. Can someone point me to where the difference is distinguished in the C++ standard?

Quote:

Originally Posted by Dave_Sinkula

No. It compiles in C, but not in C++.

So the braces for a scalar are optional in C?

Quote:

Originally Posted by swoopy

So the braces for a scalar are optional in C?

Yes, as indicated by the title of that document.

If that's the case, then why not just fix the braces to conform to C++? I guess that's been my point all along. Yes, I guess he/she can compile it as C, but that doesn't seem like a good idea if he/she plans on using C++ features.

Also the file has a cpp extension.

Quote:

Originally Posted by swoopy

If that's the case, then why not just fix the braces to conform to C++? I guess that's been my point all along. Yes, I guess he/she can compile it as C, but that doesn't seem like a good idea if he/she plans on using C++ features.

Yet again, I am not disputing this.

My comment was merely in regard to a reference to the place in which the C++ standard documents this difference. Am I making myself remotely clear yet, or should I just hang it up as a miserable attempt at something I thought might be relatively simple?

Quote:

Originally Posted by swoopy

Also the file has a cpp extension.

Duh.

I believe I get a warning why I use the -std=c90 in C++, but I guess it would be worth a try.

>Duh.
Dave you really don't have to make fun of me. I've contributed to this board over the years, there's no need to be condescending.

So C does this, C++ does that.

Quote:

Originally Posted by Dave_Sinkula

Hm. Looks like another difference between C and C++. Anyone with C&V? [Feeling lazy.]

Do you understand? The C&V is in regard to C++.

Quote:

Originally Posted by swoopy

I believe I get a warning why I use the -std=c90 in C++, but I guess it would be worth a try.

There was a 1990 C++ standard? [edit]Note: warning/error.[/edit]

Quote:

Originally Posted by swoopy

>Duh.
Dave you really don't have to make fun of me. I've contributed to this board over the years, there's no need to be condescending.

You've been trying doing it to to me in several posts already.

Compilable C:

Code:

#include <stdio.h> typedef unsigned char UInt8; typedef unsigned short UInt16; typedef unsigned long UInt32; struct HwrM68328Type { UInt8 scr; /* $000: System Control Register*/ UInt8 ___filler0[0x004-0x001]; /* The following ID stuff is not present on earlier chips (before ??)*/ UInt8 chipID; /* $004: Chip ID Register*/ UInt8 maskID; /* $005: Mask ID Register*/ UInt16 swID; /* $006: Software ID Register*/ UInt8 ___filler1[0x100-0x008]; UInt16 csAGroupBase; /* $100: Chip Select Group A Base Register*/ UInt16 csBGroupBase; /* $102: Chip Select Group B Base Register*/ UInt16 csCGroupBase; /* $104: Chip Select Group C Base Register*/ UInt16 csDGroupBase; /* $106: Chip Select Group D Base Register*/ UInt16 csAGroupMask; /* $108: Chip Select Group A Mask Register*/ UInt16 csBGroupMask; /* $10A: Chip Select Group B Mask Register*/ UInt16 csCGroupMask; /* $10C: Chip Select Group C Mask Register*/ UInt16 csDGroupMask; /* $10E: Chip Select Group D Mask Register*/ UInt32 csASelect0; /* $110: Group A Chip Select 0 Register*/ UInt32 csASelect1; /* $114: Group A Chip Select 1 Register*/ UInt32 csASelect2; /* $118: Group A Chip Select 2 Register*/ UInt32 csASelect3; /* $11C: Group A Chip Select 3 Register*/ UInt32 csBSelect0; /* $120: Group B Chip Select 0 Register*/ UInt32 csBSelect1; /* $124: Group B Chip Select 1 Register*/ UInt32 csBSelect2; /* $128: Group B Chip Select 2 Register*/ UInt32 csBSelect3; /* $12C: Group B Chip Select 3 Register*/ UInt32 csCSelect0; /* $130: Group C Chip Select 0 Register*/ UInt32 csCSelect1; /* $134: Group C Chip Select 1 Register*/ UInt32 csCSelect2; /* $138: Group C Chip Select 2 Register*/ UInt32 csCSelect3; /* $13C: Group C Chip Select 3 Register*/ UInt32 csDSelect0; /* $140: Group D Chip Select 0 Register*/ UInt32 csDSelect1; /* $144: Group D Chip Select 1 Register*/ UInt32 csDSelect2; /* $148: Group D Chip Select 2 Register*/ UInt32 csDSelect3; /* $14C: Group D Chip Select 3 Register*/ UInt16 csDebug; /* $150: Chip Select debug register*/ UInt8 ___filler2[0x200-0x152]; UInt16 pllControl; /* $200: PLL Control Register*/ UInt16 pllFreqSel; /* $202: PLL Frequency Select Register*/ UInt16 pllTest; /* $204: PLL Test Register*/ UInt8 __filler44; UInt8 pwrControl; /* $207: Power Control Register*/ UInt8 ___filler3[0x300-0x208]; UInt8 intVector; /* $300: Interrupt Vector Register*/ UInt8 ___filler4; UInt16 intControl; /* $302: Interrupt Control Register*/ UInt16 intMaskHi; /* $304: Interrupt Mask Register/HIGH word*/ UInt16 intMaskLo; /* $306: Interrupt Mask Register/LOW word*/ UInt16 intWakeupEnHi; /* $308: Interrupt Wakeup Enable Register*/ UInt16 intWakeupEnLo; /* $30A: Interrupt Wakeup Enable Register*/ UInt16 intStatusHi; /* $30C: Interrupt Status Register/HIGH word*/ UInt16 intStatusLo; /* $30E: Interrupt Status Register/LOW word*/ UInt16 intPendingHi; /* $310: Interrupt Pending Register*/ UInt16 intPendingLo; /* $312: Interrupt Pending Register*/ UInt8 ___filler4a[0x400-0x314]; UInt8 portADir; /* $400: Port A Direction Register*/ UInt8 portAData; /* $401: Port A Data Register*/ UInt8 ___filler5; UInt8 portASelect; /* $403: Port A Select Register*/ UInt8 ___filler6[4]; UInt8 portBDir; /* $408: Port B Direction Register*/ UInt8 portBData; /* $409: Port B Data Register*/ UInt8 ___filler7; UInt8 portBSelect; /* $40B: Port B Select Register */ UInt8 ___filler8[4]; UInt8 portCDir; /* $410: Port C Direction Register*/ UInt8 portCData; /* $411: Port C Data Register*/ UInt8 ___filler9; UInt8 portCSelect; /* $413: Port C Select Register */ UInt8 ___filler10[4]; UInt8 portDDir; /* $418: Port D Direction Register*/ UInt8 portDData; /* $419: Port D Data Register*/ UInt8 portDPullupEn; /* $41A: Port D Pull-up Enable*/ UInt8 ___filler11; UInt8 portDPolarity; /* $41C: Port D Polarity Register*/ UInt8 portDIntReqEn; /* $41D: Port D Interrupt Request Enable*/ UInt8 ___filler12; UInt8 portDIntEdge; /* $41F: Port D IRQ Edge Register*/ UInt8 portEDir; /* $420: Port E Direction Register*/ UInt8 portEData; /* $421: Port E Data Register*/ UInt8 portEPullupEn; /* $422: Port E Pull-up Enable*/ UInt8 portESelect; /* $423: Port E Select Register*/ UInt8 ___filler14[4]; UInt8 portFDir; /* $428: Port F Direction Register*/ UInt8 portFData; /* $429: Port F Data Register*/ UInt8 portFPullupEn; /* $42A: Port F Pull-up Enable*/ UInt8 portFSelect; /* $42B: Port F Select Register*/ UInt8 ___filler16[4]; UInt8 portGDir; /* $430: Port G Direction Register*/ UInt8 portGData; /* $431: Port G Data Register*/ UInt8 portGPullupEn; /* $432: Port G Pull-up Enable*/ UInt8 portGSelect; /* $433: Port G Select Register*/ UInt8 ___filler18[4]; UInt8 portJDir; /* $438: Port J Direction Register*/ UInt8 portJData; /* $439: Port J Data Register*/ UInt8 ___filler19; UInt8 portJSelect; /* $43B: Port J Select Register*/ UInt8 ___filler19a[4]; UInt8 portKDir; /* $440: Port K Direction Register*/ UInt8 portKData; /* $441: Port K Data Register*/ UInt8 portKPullupEn; /* $442: Port K Pull-up Enable*/ UInt8 portKSelect; /* $443: Port K Select Register*/ UInt8 ___filler21[4]; UInt8 portMDir; /* $448: Port M Direction Register*/ UInt8 portMData; /* $449: Port M Data Register*/ UInt8 portMPullupEn; /* $44A: Port M Pull-up Enable Register*/ UInt8 portMSelect; /* $44B: Port M Select Register*/ UInt8 ___filler22[4]; UInt8 ___filler23[0x500-0x450]; UInt16 pwmControl; /* $500: PWM Control Register*/ UInt16 pwmPeriod; /* $502: PWM Period Register*/ UInt16 pwmWidth; /* $504: PWM Width Register*/ UInt16 pwmCounter; /* $506: PWM Counter*/ UInt8 ___filler24[0x600-0x508]; UInt16 tmr1Control; /* $600: Timer 1 Control Register*/ UInt16 tmr1Prescaler; /* $602: Timer 1 Prescaler Register*/ UInt16 tmr1Compare; /* $604: Timer 1 Compare Register*/ UInt16 tmr1Capture; /* $606: Timer 1 Capture Register*/ UInt16 tmr1Counter; /* $608: Timer 1 Counter Register*/ UInt16 tmr1Status; /* $60A: Timer 1 Status Register*/ UInt16 tmr2Control; /* $60C: Timer 2 Control Register*/ UInt16 tmr2Prescaler; /* $60E: Timer 2 Prescaler Register*/ UInt16 tmr2Compare; /* $610: Timer 2 Compare Register*/ UInt16 tmr2Capture; /* $612: Timer 2 Capture Register*/ UInt16 tmr2Counter; /* $614: Timer 2 Counter Register*/ UInt16 tmr2Status; /* $616: Timer 2 Status Register*/ UInt16 wdControl; /* $618: Watchdog Control Register*/ UInt16 wdReference; /* $61A: Watchdog Reference Register*/ UInt16 wdCounter; /* $61C: Watchdog Counter*/ UInt8 ___filler25[0x700-0x61E]; UInt16 spiSlave; /* $700: SPI Slave Register*/ UInt8 ___filler26[0x800-0x702]; UInt16 spiMasterData; /* $800: SPI Master Data Register*/ UInt16 spiMasterControl; /* $802: SPI Master Control Register*/ UInt8 ___filler27[0x900-0x804]; UInt16 uControl; /* $900: Uart Control Register*/ UInt16 uBaud; /* $902: Uart Baud Control Register*/ UInt16 uReceive; /* $904: Uart Receive Register*/ UInt16 uTransmit; /* $906: Uart Transmit Register*/ UInt16 uMisc; /* $908: Uart Miscellaneous Register*/ UInt8 ___filler28[0xA00-0x90A]; UInt32 lcdStartAddr; /* $A00: Screen Starting Address Register*/ UInt8 ___filler29; UInt8 lcdPageWidth; /* $A05: Virtual Page Width Register*/ UInt8 ___filler30[2]; UInt16 lcdScreenWidth; /* $A08: Screen Width Register*/ UInt16 lcdScreenHeight; /* $A0A: Screen Height Register*/ UInt8 ___filler31[0xA18-0xA0C]; UInt16 lcdCursorXPos; /* $A18: Cursor X Position*/ UInt16 lcdCursorYPos; /* $A1A: Cursor Y Position*/ UInt16 lcdCursorWidthHeight; /* $A1C: Cursor Width and Height*/ UInt8 ___filler32; UInt8 lcdBlinkControl; /* $A1F: Blink Control Register*/ UInt8 lcdPanelControl; /* $A20: Panel Interface Control Register*/ UInt8 lcdPolarity; /* $A21: Polarity Config Register*/ UInt8 ___filler33; UInt8 lcdACDRate; /* $A23: ACD (M) Rate Control Register*/ UInt8 ___filler34; UInt8 lcdPixelClock; /* $A25: Pixel Clock Divider Register*/ UInt8 ___filler35; UInt8 lcdClockControl; /* $A27: Clocking Control Register*/ UInt8 ___filler36; UInt8 lcdLastBufferAddr; /* $A29: Last Buffer Address Register*/ UInt8 ___filler37; UInt8 lcdOctetTermCount; /* $A2B: Octet Terminal Count Register*/ UInt8 ___filler38; UInt8 lcdPanningOffset; /* $A2D: Panning Offset Register*/ UInt8 ___filler39[3]; UInt8 lcdFrameRate; /* $A31: Frame Rate Control Modulation Register*/ UInt16 lcdGrayPalette; /* $A32: Gray Palette Mapping Register*/ UInt8 lcdReserved; /* $A34: Reserved*/ UInt8 ___filler40[0xB00-0xA35]; UInt32 rtcHourMinSec; /* $B00: RTC Hours, Minutes, Seconds Register*/ UInt32 rtcAlarm; /* $B04: RTC Alarm Register*/ UInt32 rtcReserved; /* $B08: RTC Reserved*/ UInt16 rtcControl; /* $B0C: RTC Control Register*/ UInt16 rtcIntStatus; /* $B0E: RTC Interrupt Status Register*/ UInt16 rtcIntEnable; /* $B10: RTC Interrupt Enable Register*/ UInt16 stopWatch; /* $B12: Stopwatch Minutes*/ }; const struct HwrM68328Type kInitial68328RegisterValues = { 0x0C, /* Byte scr; // $000: System Control Register*/ { 0 }, /* Byte ___filler0[0x004-0x001];*/ /* The following ID stuff is not present on earlier chips (before ??)*/ 0,/*hwr328chipID328, /* Byte chipID; // $004: Chip ID Register*/ 0,/*hwr328maskID1H58B, /* Byte maskID; // $005: Mask ID Register*/ 0x00, /* Word swID; // $006: Software ID Register*/ { 0 }, /* Byte ___filler1[0x100-0x008]; */ 0x0000, /* Word csAGroupBase; // $100: Chip Select Group A Base Register*/ 0x0000, /* Word csBGroupBase; // $102: Chip Select Group B Base Register*/ 0x0000, /* Word csCGroupBase; // $104: Chip Select Group C Base Register*/ 0x0000, /* Word csDGroupBase; // $106: Chip Select Group D Base Register*/ 0x0000, /* Word csAGroupMask; // $108: Chip Select Group A Mask Register*/ 0x0000, /* Word csBGroupMask; // $10A: Chip Select Group B Mask Register*/ 0x0000, /* Word csCGroupMask; // $10C: Chip Select Group C Mask Register*/ 0x0000, /* Word csDGroupMask; // $10E: Chip Select Group D Mask Register*/ 0x00010006, /* DWord csASelect0; // $110: Group A Chip Select 0 Register*/ 0x00010006, /* DWord csASelect1; // $114: Group A Chip Select 1 Register*/ 0x00010006, /* DWord csASelect2; // $118: Group A Chip Select 2 Register*/ 0x00010006, /* DWord csASelect3; // $11C: Group A Chip Select 3 Register*/ 0x00000000, /* DWord csBSelect0; // $120: Group B Chip Select 0 Register*/ 0x00000000, /* DWord csBSelect1; // $124: Group B Chip Select 1 Register*/ 0x00000000, /* DWord csBSelect2; // $128: Group B Chip Select 2 Register*/ 0x00000000, /* DWord csBSelect3; // $12C: Group B Chip Select 3 Register*/ 0x00010006, /* DWord csCSelect0; // $130: Group C Chip Select 0 Register*/ 0x00010006, /* DWord csCSelect1; // $134: Group C Chip Select 1 Register*/ 0x00010006, /* DWord csCSelect2; // $138: Group C Chip Select 2 Register*/ 0x00010006, /* DWord csCSelect3; // $13C: Group C Chip Select 3 Register*/ 0x00000000, /* DWord csDSelect0; // $140: Group D Chip Select 0 Register*/ 0x00000000, /* DWord csDSelect1; // $144: Group D Chip Select 1 Register*/ 0x00000000, /* DWord csDSelect2; // $148: Group D Chip Select 2 Register*/ 0x00000000, /* DWord csDSelect3; // $14C: Group D Chip Select 3 Register*/ 0x0000, /* Word csDebug; // $150: Chip Select debug register*/ { 0 }, /* Byte ___filler2[0x200-0x152];*/ 0x2400, /* Word pllControl; // $200: PLL Control Register*/ 0x0123, /* Word pllFreqSel; // $202: PLL Frequency Select Register*/ 0x0000, /* Word pllTest; // $204: PLL Test Register*/ { 0 }, /* Byte __filler44;*/ 0x1F, /* Byte pwrControl; // $207: Power Control Register*/ { 0 }, /* Byte ___filler3[0x300-0x208];*/ 0x00, /* Byte intVector; // $300: Interrupt Vector Register*/ { 0 }, /* Byte ___filler4;*/ 0x0000, /* Word intControl; // $302: Interrupt Control Register*/ 0x00FF, /* Word intMaskHi; // $304: Interrupt Mask Register/HIGH word*/ 0xFFFF, /* Word intMaskLo; // $306: Interrupt Mask Register/LOW word*/ 0x00FF, /* Word intWakeupEnHi; // $308: Interrupt Wakeup Enable Register*/ 0xFFFF, /* Word intWakeupEnLo; // $30A: Interrupt Wakeup Enable Register*/ 0x0000, /* Word intStatusHi; // $30C: Interrupt Status Register/HIGH word*/ 0x0000, /* Word intStatusLo; // $30E: Interrupt Status Register/LOW word*/ 0x0000, /* Word intPendingHi; // $310: Interrupt Pending Register*/ 0x0000, /* Word intPendingLo; // $312: Interrupt Pending Register*/ { 0 }, /* Byte ___filler4a[0x400-0x314];*/ 0x00, /* Byte portADir; // $400: Port A Direction Register*/ 0x00, /* Byte portAData; // $401: Port A Data Register*/ { 0 }, /* Byte ___filler5;*/ 0x00, /* Byte portASelect; // $403: Port A Select Register*/ { 0 }, /* Byte ___filler6[4];*/ 0x00, /* Byte portBDir; // $408: Port B Direction Register*/ 0x00, /* Byte portBData; // $409: Port B Data Register*/ { 0 }, /* Byte ___filler7;*/ 0x00, /* Byte portBSelect; // $40B: Port B Select Register*/ { 0 }, /* Byte ___filler8[4];*/ 0x00, /* Byte portCDir; // $410: Port C Direction Register*/ 0x00, /* Byte portCData; // $411: Port C Data Register*/ { 0 }, /* Byte ___filler9;*/ 0x00, /* Byte portCSelect; // $413: Port C Select Register*/ { 0 }, /* Byte ___filler10[4];*/ 0x00, /* Byte portDDir; // $418: Port D Direction Register*/ 0x00, /* Byte portDData; // $419: Port D Data Register*/ 0xFF, /* Byte portDPullupEn; // $41A: Port D Pull-up Enable*/ { 0 }, /* Byte ___filler11;*/ 0x00, /* Byte portDPolarity; // $41C: Port D Polarity Register*/ 0x00, /* Byte portDIntReqEn; // $41D: Port D Interrupt Request Enable*/ { 0 }, /* Byte ___filler12;*/ 0x00, /* Byte portDIntEdge; // $41F: Port D IRQ Edge Register*/ 0x00, /* Byte portEDir; // $420: Port E Direction Register*/ 0x00, /* Byte portEData; // $421: Port E Data Register*/ 0x80, /* Byte portEPullupEn; // $422: Port E Pull-up Enable*/ 0x80, /* Byte portESelect; // $423: Port E Select Register*/ { 0 }, /* Byte ___filler14[4];*/ 0x00, /* Byte portFDir; // $428: Port F Direction Register*/ 0x00, /* Byte portFData; // $429: Port F Data Register*/ 0xFF, /* Byte portFPullupEn; // $42A: Port F Pull-up Enable*/ 0xFF, /* Byte portFSelect; // $42B: Port F Select Register*/ { 0 }, /* Byte ___filler16[4];*/ 0x00, /* Byte portGDir; // $430: Port G Direction Register*/ 0x00, /* Byte portGData; // $431: Port G Data Register*/ 0xFF, /* Byte portGPullupEn; // $432: Port G Pull-up Enable*/ 0xFF, /* Byte portGSelect; // $433: Port G Select Register*/ { 0 }, /* Byte ___filler18[4];*/ 0x00, /* Byte portJDir; // $438: Port J Direction Register*/ 0x00, /* Byte portJData; // $439: Port J Data Register*/ { 0 }, /* Byte ___filler19;*/ 0x00, /* Byte portJSelect; // $43B: Port J Select Register*/ { 0 }, /* Byte ___filler19a[4];*/ 0x00, /* Byte portKDir; // $440: Port K Direction Register*/ 0x00, /* Byte portKData; // $441: Port K Data Register*/ 0x3F, /* Byte portKPullupEn; // $442: Port K Pull-up Enable*/ 0x3F, /* Byte portKSelect; // $443: Port K Select Register*/ { 0 }, /* Byte ___filler21[4];*/ 0x00, /* Byte portMDir; // $448: Port M Direction Register*/ 0x00, /* Byte portMData; // $449: Port M Data Register*/ 0xFF, /* Byte portMPullupEn; // $44A: Port M Pull-up Enable Register*/ 0x02, /* Byte portMSelect; // $44B: Port M Select Register*/ { 0 }, /* Byte ___filler22[4];*/ { 0 }, /* Byte ___filler23[0x500-0x450];*/ 0x0000, /* Word pwmControl; // $500: PWM Control Register*/ 0x0000, /* Word pwmPeriod; // $502: PWM Period Register*/ 0x0000, /* Word pwmWidth; // $504: PWM Width Register*/ 0x0000, /* Word pwmCounter; // $506: PWM Counter*/ { 0 }, /* Byte ___filler24[0x600-0x508];*/ 0x0000, /* Word tmr1Control; // $600: Timer 1 Control Register*/ 0x0000, /* Word tmr1Prescaler; // $602: Timer 1 Prescaler Register*/ 0xFFFF, /* Word tmr1Compare; // $604: Timer 1 Compare Register*/ 0x0000, /* Word tmr1Capture; // $606: Timer 1 Capture Register*/ 0x0000, /* Word tmr1Counter; // $608: Timer 1 Counter Register*/ 0x0000, /* Word tmr1Status; // $60A: Timer 1 Status Register*/ 0x0000, /* Word tmr2Control; // $60C: Timer 2 Control Register*/ 0x0000, /* Word tmr2Prescaler; // $60E: Timer 2 Prescaler Register*/ 0xFFFF, /* Word tmr2Compare; // $610: Timer 2 Compare Register*/ 0x0000, /* Word tmr2Capture; // $612: Timer 2 Capture Register*/ 0x0000, /* Word tmr2Counter; // $614: Timer 2 Counter Register*/ 0x0000, /* Word tmr2Status; // $616: Timer 2 Status Register*/ 0x0000, /* Word wdControl; // $618: Watchdog Control Register*/ 0x0000, /* Word wdReference; // $61A: Watchdog Reference Register*/ 0x0000, /* Word wdCounter; // $61C: Watchdog Counter*/ { 0 }, /* Byte ___filler25[0x700-0x61E];*/ 0x0000, /* Word spiSlave; // $700: SPI Slave Register*/ { 0 }, /* Byte ___filler26[0x800-0x702];*/ 0x0000, /* Word spiMasterData; // $800: SPI Master Data Register*/ 0x0000, /* Word spiMasterControl; // $802: SPI Master Control Register*/ { 0 }, /* Byte ___filler27[0x900-0x804];*/ 0x0000, /* Word uControl; // $900: Uart Control Register*/ 0x003F, /* Word uBaud; // $902: Uart Baud Control Register*/ 0x0000, /* Word uReceive; // $904: Uart Receive Register*/ 0x0000, /* Word uTransmit; // $906: Uart Transmit Register*/ 0x0000, /* Word uMisc; // $908: Uart Miscellaneous Register*/ { 0 }, /* Byte ___filler28[0xA00-0x90A];*/ 0x00000000, /* DWord lcdStartAddr; // $A00: Screen Starting Address Register*/ { 0 }, /* Byte ___filler29;*/ 0xFF, /* Byte lcdPageWidth; // $A05: Virtual Page Width Register*/ { 0 }, /* Byte ___filler30[2];*/ 0x03FF, /* Word lcdScreenWidth; // $A08: Screen Width Register*/ 0x01FF, /* Word lcdScreenHeight; // $A0A: Screen Height Register*/ { 0 }, /* Byte ___filler31[0xA18-0xA0C];*/ 0x0000, /* Word lcdCursorXPos; // $A18: Cursor X Position*/ 0x0000, /* Word lcdCursorYPos; // $A1A: Cursor Y Position*/ 0x0101, /* Word lcdCursorWidthHeight; // $A1C: Cursor Width and Height*/ { 0 }, /* Byte ___filler32;*/ 0x7F, /* Byte lcdBlinkControl; // $A1F: Blink Control Register*/ 0x00, /* Byte lcdPanelControl; // $A20: Panel Interface Control Register*/ 0x00, /* Byte lcdPolarity; // $A21: Polarity Config Register*/ 0x00, /* Byte ___filler33;*/ 0x00, /* Byte lcdACDRate; // $A23: ACD (M) Rate Control Register*/ 0x00, /* Byte ___filler34;*/ 0x00, /* Byte lcdPixelClock; // $A25: Pixel Clock Divider Register*/ 0x00, /* Byte ___filler35;*/ 0x40, /* Byte lcdClockControl; // $A27: Clocking Control Register*/ 0x00, /* Byte ___filler36;*/ 0x3E, /* Byte lcdLastBufferAddr; // $A29: Last Buffer Address Register*/ 0x00, /* Byte ___filler37;*/ 0x3F, /* Byte lcdOctetTermCount; // $A2B: Octet Terminal Count Register*/ 0x00, /* Byte ___filler38;*/ 0x00, /* Byte lcdPanningOffset; // $A2D: Panning Offset Register*/ { 0 }, /* Byte ___filler39[3];*/ 0xB9, /* Byte lcdFrameRate; // $A31: Frame Rate Control Modulation Register*/ 0x1073, /* Word lcdGrayPalette; // $A32: Gray Palette Mapping Register*/ 0x00, /* Byte lcdReserved; // $A34: Reserved*/ { 0 }, /* Byte ___filler40[0xB00-0xA35];*/ 0x00000000, /* DWord rtcHourMinSec; // $B00: RTC Hours, Minutes, Seconds Register*/ 0x00000000, /* DWord rtcAlarm; // $B04: RTC Alarm Register*/ 0x00000000, /* DWord rtcReserved; // $B08: RTC Reserved*/ 0x0000, /* Word rtcControl; // $B0C: RTC Control Register*/ 0x0000, /* Word rtcIntStatus; // $B0E: RTC Interrupt Status Register*/ 0x0000, /* Word rtcIntEnable; // $B10: RTC Interrupt Enable Register*/ 0x0000 /* Word stopWatch; // $B12: Stopwatch Minutes*/ }; /*line 321*/ int main(void) { puts("hello world"); return 0; }

Not so in C++.

No, maybe it was obvious to you when you posted, but you never said the code the OP posted compiles as C. You just said there's a difference. Well what difference?

>here was a 1990 C++ standard?
No that switch is for Dev-C++, specified as compiler options. There is no separate C compiler options, and C++ compiler options.

Quote:

Originally Posted by swoopy

No, maybe it was obvious to you when you posted, but you never said the code the OP posted compiles as C. You just said there's a difference. Well what difference?

Let me attempt to rephrase once again. The C standards allows scalars to be optionally enclosed in braces. C++ apparently does not allow this. Can anyone point me to where this is documented?

Thus the question...

Quote:

Originally Posted by Dave_Sinkula

Hm. Looks like another difference between C and C++. Anyone with C&V? [Feeling lazy.]

After an attempt at clarification...

Quote:

Originally Posted by Dave_Sinkula

The C&V is in regard to C++.

I think why you got upset was I missed your point when you said: another difference between C and C++. Obviously I didn't get it. Maybe I'll learn to read between the lines eventually, and realize what you meant was: Guess what, this code compiles in C. But unfortunately I missed you implication, and it led to a blowup. Oh well, I'm sorry about that.

If the compiler you just used can compile C++, it would be interesting to see what happens. I'll try it with Dev-C++ tomorrow, just for curiosity.

Quote:

Originally Posted by swoopy

I think why you got upset was I missed your point when you said: another difference between C and C++. Obviously I didn't get it. Maybe I'll learn to read between the lines eventually, and realize what you meant was: Guess what, this code compiles in C. But unfortunately I missed you implication, and it led to a blowup. Oh well, I'm sorry about that.

I was irritated by a separate thread to imply that I was blind. I've considered your longstanding contributions in my many posts to this thread in an attempt to hold my ground and ask the question I was asking, and at the same time keep you from derailing it. I dunno. I've probably failed on both issues.

[edit]

Quote:

Originally Posted by swoopy

If the compiler you just used can compile C++, it would be interesting to see what happens. I'll try it with Dev-C++ tomorrow, just for curiosity.

For me, the curiosity was the reverse: compiling as C.

>I was irritated by a separate thread to imply that I was blind.
Well that was really meant for the thread as a whole. If you take the initial premise that the code would not compile for the OP, then what is the solution? I felt the solution was to remove the offending braces (the braces for members which were not array items), whether the C++ standard said to or not. I guess I was wrong.

I can confirm that compiling Dave_Sinkula's sample code with the MinGW port of gcc 3.4.2 gives warnings about "braces around scalar initializer". Compiling with g++ instead gives errors about "brace-enclosed initializer used to initialize 'UInt8'".

Section 8.5 of the C++ Standard states:

Quote:

If T is a scalar type, then a declaration of the form

Code:

T x = { a };

is equivalent to

Code:

T x = a;

Hmm, that's curious. So according to the C++ standard it should compile, but g++ does not like it. And gcc 3.4.2 accepts it, but issues warnings. Strange indeed.

Oh, but the plot thickens. I am probably missing some obvious text in the standard, as the online Comeau compiler tells me:

Code:

Comeau C/C++ 4.3.9 (Mar 27 2007 17:24:47) for ONLINE_EVALUATION_BETA1 Copyright 1988-2007 Comeau Computing. All rights reserved. MODE:strict errors C++ C++0x_extensions "ComeauTest.c", line 9: error: extra braces are nonstandard Test test = {1, {2}}; ^ "ComeauTest.c", line 9: warning: variable "test" was declared but never referenced Test test = {1, {2}}; ^ 1 error detected in the compilation of "ComeauTest.c".

For the test code:

Code:

struct Test { int x; int y; }; int main() { Test test = {1, {2}}; }

I tried your test code with Borland, and it compiles without warnings in both C++ mode and C mode (with minor changes). Actually there were warnings, but not pertaining to the struct. I'll try it with Dev-C++ later today, but expect to get the same result you got Lasarlight with MinGW.

My theory is that in this context Comeau and other compilers are expecting nested structures or an array here, where braces would be okay. It could also be reasonably disputed that despite ints being scalar, a structure is not, and therefore extra braces are non-standard. But there is some safe leeway here, so I doubt it matters tremendously. If the compiler complains, you can delete the braces right?

Whether this rule is something that was introduced with C++ or simply not enforced in standard C is something beyond my knowledge right now.

I was doing some searching earlier in the day and discovered some things regarding my threadjacking here.

I tried the Comeau compiler, but was having issues with C++ options for C compiling, so I asked them about this as well. Some selected quotes:

Quote:

>Essentially it involves "The initializer for a scalar shall be a
>single expression, optionally enclosed in braces."
>http://web.archive.org/web/200502070...aft.html#3.5.7

That's misleading words probably, since we recall a paragraph or two
later there is more words basically saying "... and if it is an
aggregate... do this instead" hence in contrast the the scalar.

>If you don't mind wandering through an existing thread for further
>clarification, my curiousity with this issue started about here:
>http://cboard.cprogramming.com/showt...083#post640083 or
>http://cboard.cprogramming.com/showt...125#post640125

Generally, C and C++ should be saying the same things, except (and
this is off the top of our heads) they don't use exactly the same
words, each has had their wording tweaking as per their respective
defect reports processing, and also, seem to recall C++ explicitly
makes some of the case ill-formed, whereas in C it's left
undefined. Probably in both cases, the problem boils down to that
the wording probably lead into that there is an extra initializer
being brought forth (the scalar member is left unitialized, and then
the {}s try to init a non-existant sub-aggregate). Either that, or
you've found a problem with both standards.

Quote:

> > Well, at least in one you're comparing two different things:
> >
> > int x = { 42 };
> >
> > is allowed in C++. But as mentioned, we recall it's ill-formed when
> > used as an aggregate initializer. The words to handle this is both
> > standards are not fun, so as mentioned, it good be there is a problem
> > with the words.
>
>Okay, so is it that scalar *members* of aggregates do not allow this?

We think it could be worded clearer, but yes, we believe that is the
intention.

Quote:

FWIW, we recalled this
http://www.comeaucomputing.com/iso/cwg_defects.html#163 We'll need
to review which side of the fence this leaves/brings the situation :)

And some other searching got me to the C90 rationale:

Quote:

Various implementations have parsed aggregate initializers with partially elided braces differently. The Standard has reaffirmed the (top-down) parse described in the Base Document. Although the construct is allowed, and its parse well defined, the Committee urges programmers to avoid partially elided initializers: such initializations can be quite confusing to read.

QUIET CHANGE

Code which relies on a bottom-up parse of aggregate initializers with partially elided braces will not yield the expected initialized object.

And this interesting number from Sun's documention:

Quote:

[ISO C]Uses a top-down parsing algorithm. For example:

Code:

struct{int a[3];int b;}\ w[]={{1},2};

yields

Code:

sizeof(w)=32 w[0].a=1,0,0 w[0].b=0 w[1].a=2,0,0 w[1].b=0

[K&R]Uses a bottom-up algorithm when parsing and processing partially elided initializers within braces:

Code:

struct{ int a[3]; int b; }\ w[]={{1},2};

yields

Code:

sizeof(w)=16 w[0].a=1,0,0 w[0].b=2

Experimenting with my newly-learned term, "partially elided braces", and from Sun's docs, I just had to give this a go:

Code:

#include <stdio.h> int main(void) { struct { int a[3]; int b; } w[] = { { { 1 }, 2 } }, x[] = { { 1 }, 2 }; printf("sizeof w = %lu\n", (long unsigned)sizeof w); printf("sizeof x = %lu\n", (long unsigned)sizeof x); return 0; } /* sizeof w = 16 sizeof x = 32 */

I believe I've already mentioned the defect, but it is also here.

And another related thread I found along the way.

FWIW

[edit]Oh, and regarding my issue with the online compiler:

Quote:

>http://www.redacted.com/

That's a dead link. But we put two and two together and figured out
that C++ extensions were being requested in some C modes. It should
now be ok.

I ran your sample code through Borland, and the output was the same (16 and 32).

Lots of food for thought there Dave, I'm still reading some of it. Near as I can tell, Comeau thinks its compiler is correct, but they can't quite explain why. I'll reread some of this tomorrow. Maybe it'll make more sense.

It does seem to make sense that the output for the sample code is 16 and 32, given that the standards committee says the parse is top-down. So each time you encounter a left-brace, that's a new subobject.

More digging...

Standard C/Bugs

Quote:

[...]

So for all these reasons, I stuffed the library through a C++ compiler and shook out the nits. Two language differences led to numerous changes. One was the meaning of void pointers. The other was the use of braces in initializers.

[...]

The third largest batch was data initializers. I found that I had much less latitude in writing braces in C++ than in C. Partially bracketed initializers are a no-no. But so too are braces around a scalar initializer, as in:

Code:

static const double sqrt2 = {1.41421356237309505}; /* BAD C++ */

I still don't know whether this is a C++ requirement or a peculiarity of Turbo C++. I haven't read the draft C++ standard in sufficient detail to find out. In either event, I figure that the tighter rules are probably a good idea. C compilers have been notoriously inconsistent in how they interpret initializers with elided braces. Even the C Standard seems to confuse more people than it helps in this area.

C++ Standard Core Language Active Issues, Revision 46

Quote:

155. Brace initializer for scalar

Section: 8.5 dcl.init <http://www.open-std.org/jtc1/sc22/wg21/docs/decl.html#dcl.init> Status: open Submitter: Steve Clamage Date: 12 Aug 1999

It is not clear whether the following declaration is well-formed:

Code:

struct S { int i; } s = { { 1 } };

According to 8.5.1 dcl.init.aggr <http://www.open-std.org/jtc1/sc22/wg21/docs/decl.html#dcl.init.aggr> paragraph 2, a brace-enclosed initializer is permitted for a subaggregate of an aggregate; however, i is a scalar, not an aggregate. 8.5 dcl.init <http://www.open-std.org/jtc1/sc22/wg21/docs/decl.html#dcl.init> paragraph 13 says that a standalone declaration like

Code:

int i = { 1 };

is permitted, but it is not clear whether this says anything about the form of initializers for scalar members of aggregates.

This is (more) clearly permitted by the C89 Standard.

But essentially I believe my questions are answered:

C and C++ do differ when it comes to partially elided braces.
Scalar members of aggregates don't have the same optional braces rule for initializers as "plain" scalars.
My main interest was in a construct like this:

Code:

type value = {0};

I had come to understand it as a "magic" construct that worked for all types.

Well, it's still true in that respect and for both languages, but now I know that this doesn't extended to members of an aggregate or union. (Well, I suppose a union might have possible issues. And the compiler may still dispatch good-intentioned warnings.)

---

This issue appears to have already come up with the C++ folks. And the confusing stuff I failed to parse in the C standard is apparently that way by design. :p