creating make files

can someone please give me an example of a makefile. what i am trying to do is compile two files with gcc by using the make comand. right now i have

all:
gcc -o file1 file1.c
gcc -o file2 file2.c


and if i issue the make command i get

make: Fatal error in reader: Makefile, line 3: Unexpected end of line seen

help!!!
thanks.

Are you trying to compile two programs, or simply compile a single program that has two .c source files?

Either way, you're not supposed to generate the Makefile yourself. You generate the Makefile.am and the configure.in(I think. There might be programs to help. I'm rather new to programming in Linux).

type:
$info automake

In the former case, examples->ctags&etags is a good example.

In the latter case, either use a different example or just read the rest of the docs(which are better than your average info help).

Actually,
You can and should create your own make file. Just to be sure you know what you want.

I'm using Redhat Linux 6.2 on an i686
not sure if that would affect your makefile any, but the type of OS you are running would no doubt have an effect on the syntax of the things you use.

Here's a look at my makefile.

Code:

---

CC      = gcc
PROF    =
OPTOMIZ = -O2
DEBUG  = -g3
WARN    = -Wall
#C_FLAGS = $(PROF) $(OPTOMIZ) $(WARN) $(DEBUG)
C_FLAGS = -c -O -Wall -g3
L_FLAGS = -static -g
CRYPT  = -lcrypt
SYSTEM  =

O_FILES = act_comm.o act_info.o act_move.o blah blah blah
(i'm not sure you need the names of my '.o' files... but here is wher you put your files to be compiled)  be sure to leave a '~' at the end or bad things will happen ;)

---

I'm also using the concurrent versioning system (CVS) so things are subject to changes if you are not.

HTH

Your best bet is to be very specific and break it down into the separate parts.

Code:

---

#######################################
#
# Makefile
#

FILES = file1.c file2.c

OBJECTS = file1.o file2.o

all:      $(OBJECTS)
          gcc -o NameOfExecutable $(OBJECTS)

file1.o:  $(FILES) $(OBJECTS)
          gcc -c file1.c

file2.o:  $(FILES) $(OBJECTS)
          gcc -c file2.c

---

Also make certain there is no CrLf after the last item.

David

a simple hint with the last example



parameter_name : dependent files (a.out and the files you'll use )
<tab very imp ok> commands



enjoy