Makefile Problem: None rule to make target

This is a discussion on Makefile Problem: None rule to make target within the Linux Programming forums, part of the Platform Specific Boards category; Hello, I am working with robotics (Koala from K-Team if it matters) and i'm trying to compile some code. The ...

  1. #1
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    Makefile Problem: None rule to make target

    Hello, I am working with robotics (Koala from K-Team if it matters) and i'm trying to compile some code. The robot has arm linux on it. I am trying to use some low level calls but when I try to compile make returns with no rule to make target. I'm still adapting to using linux and make. Now, my directory structure is setup like so, my code and makefile are in the folder and then there is an additional folder where all the robot specific files are. I had another makefile to use as a guide but it was just a basic makefile, so I have been modifying it trying to get it to work but still no luck. I tried changing the paths to the folder i mentioned in my directory with my src but that still did not work. My dependency files are already compiled from a previous date and they are not going to be modified in the future. My makefile is below.

    Code:
    Code:
    all: ks knet_rs232.o knet.o koala.o
    
    # Got to use the right tools
    CC              = arm-linux-gcc
    LD              = arm-linux-ld
    AR              = arm-linux-ar
    AS              = arm-linux-as
    
    KOREBOT_DIR	= /share/robots/libkorebot-1.11/build-korebot/lib/
    KOREBOT_LIB	= korebot-1.11
    KOREBOT_INC	= /share/robots/libkorebot-1.11/build-korebot/include/
    
    export PATH=/share/robots/korebot-tools-2.1/bin:$PATH
    
    #
    # Start the rules 
    #
    
    ks: KoalaT.c knet_rs232.o knet.o koala.o
    	$(CC) KoalaT.c knet.o koala.o knet_rs232.o -o KoalaT -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB) -lm
    
    knet_rs232.o: knet_rs232.c knet_rs232.h
    	$(CC) -o knet_rs232.c -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    knet.o: knet.c knet.h
    	$(CC) -o knet.c -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    koala.o: koala.c koala.h
    	$(CC) -o koala.c -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    Here is my output:
    make: Warning: File `Makefile' has modification time 13 s in the future
    make: *** No rule to make target `knet_rs232.c', needed by `knet_rs232.o'. Stop.


    Can someone lead me in the right direction?

    Thanks,
    Chris
    chris24300 is online now Report Post Edit/Delete Message

  2. #2
    and the hat of wrongness Salem's Avatar
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    All your .o from .c rules need to use the -c flag (compile only)

    > -l$(KOREBOT_LIB)
    And you only need this for the final target

    Plus mixing .c and .o in the final target is messy. Create another .c.o rule for that as well.
    If you dance barefoot on the broken glass of undefined behaviour, you've got to expect the occasional cut.
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  3. #3
    Frequently Quite Prolix dwks's Avatar
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    May I suggest a Makefile template?
    Code:
    # Makefile template
    
    CC = gcc
    CFLAGS = -W -Wall -ansi -pedantic -g
    LDFLAGS =
    
    SOURCES = $(wildcard *.c)
    OBJECTS = $(SOURCES:.c=.o)
    TARGET = executable
    
    # Default target: all
    .PHONY: all
    all: $(TARGET)
    
    # Executable target
    $(TARGET): $(OBJECTS)
    	$(CC) -o $@ $^ $(LDFLAGS)
    
    # Source file dependencies
    
    include depend
    
    .PHONY: depend
    depend:
    	$(CC) -MM $(SOURCES) > depend
    
    # Miscellaneous targets
    .PHONY: clean
    clean:
    	-$(RM) $(OBJECTS) $(SOURCES)
    That automatically gathers all of the .c files in the current directory with $(wildcard *.c), or you can list each source file there if you like. The $(SOURCES:.c=.o) means to take the list of files in $(SOURCES) and replace each .c ending with .o. ".PHONY" means to always rebuild this target, even if the corresponding file exists.

    The "depend" stuff uses "gcc -MM" to automatically generate the list of dependencies. That way you don't have to figure this out yourself and write "knet_rs232.o: knet_rs232.c knet_rs232.h" etc. The dependencies are stored in the file "depend". Since it's marked with .PHONY, depend is rebuilt every time (it doesn't take very long at all).

    That Makefile uses the default .c.o target to automatically compile .c files into .o files.

    Oh, and $@ evaluates to the target name, while $^ evaluates to the list of dependencies. And the - in front of the clean target's command means to ignore errors (that way, make will exit with a successful return value even if the rm command failed -- e.g. if some files did not exist).
    dwk

    Seek and ye shall find. quaere et invenies.

    "Simplicity does not precede complexity, but follows it." -- Alan Perlis
    "Testing can only prove the presence of bugs, not their absence." -- Edsger Dijkstra
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  4. #4
    Captain Crash brewbuck's Avatar
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    Quote Originally Posted by dwks View Post
    May I suggest a Makefile template?
    Your template is similar to the one I use. However, I see a problem in your depend target -- you do not pass the CFLAGS when calling the compiler in depend mode. It doesn't usually matter, but the CFLAGS (more specifically, a preprocess define) can change the set of header files which get included, so you may end up building an incorrect dependency list.

    This is why I break my CFLAGS into multiple parts like so:

    Code:
    BASE_CFLAGS = -W -Wall
    DBGFLAGS =
    OFLAGS =
    PROFFLAGS =
    
    DEFINES = 
    INCLUDES = 
    
    PPFLAGS = $(DEFINES) $(INCLUDES)
    
    CFLAGS = $(BASE_CFLAGS) $(DBGFLAGS) $(OFLAGS) $(PROFFLAGS) $(PPFLAGS)
    
    .depend: $(SRCS) $(HDRS)
        $(CC) $(PPFLAGS) -M $(SRCS) > $@
    
    -include .depend
    This way, the same include path and set of PP defines gets used both for compiling and building the dependency list.
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

  5. #5
    Captain Crash brewbuck's Avatar
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    Quote Originally Posted by chris24300 View Post
    make: Warning: File `Makefile' has modification time 13 s in the future
    make: *** No rule to make target `knet_rs232.c', needed by `knet_rs232.o'. Stop.
    This means that the file "knet_rs232.c" does not exist.
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

  6. #6
    {Jaxom,Imriel,Liam}'s Dad Kennedy's Avatar
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    Quote Originally Posted by brewbuck View Post
    This means that the file "knet_rs232.c" does not exist.
    Or it could mean that you are on a system with an NFS mouted directory and you haven't synced the times. . .

  7. #7
    Captain Crash brewbuck's Avatar
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    Quote Originally Posted by Kennedy View Post
    Or it could mean that you are on a system with an NFS mouted directory and you haven't synced the times. . .
    But then it would just fail to update, it wouldn't report that the dependency could not be built...
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

  8. #8
    {Jaxom,Imriel,Liam}'s Dad Kennedy's Avatar
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    Quote Originally Posted by brewbuck View Post
    But then it would just fail to update, it wouldn't report that the dependency could not be built...
    Read? Me? NEVER!!!! I saw the warning and ignored the rest. . . rest, maybe that's what I need.

  9. #9
    Captain Crash brewbuck's Avatar
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    Quote Originally Posted by Kennedy View Post
    Read? Me? NEVER!!!! I saw the warning and ignored the rest. . . rest, maybe that's what I need.
    But the warning about the makefile time being in the future is definitely pertinent -- and yes, it's probably caused by the network drive having a slightly different idea of what the current time is.

    This can be extremely dangerous -- things will not rebuild that ought to rebuild. And if the output scrolls by fast enough, you may miss the warning message entirely. For development, it's a pain in the ass -- for official builds, building off anything but a local filesystem is DANGEROUS.
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

  10. #10
    Frequently Quite Prolix dwks's Avatar
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    ... This way, the same include path and set of PP defines gets used both for compiling and building the dependency list.
    Interesting. And yes, it was my mistake to leave out the $(CFLAGS). I just typed up that Makefile at the time of the post, because I can't bear to let people type out dependencies manually when gcc can do it for you.
    dwk

    Seek and ye shall find. quaere et invenies.

    "Simplicity does not precede complexity, but follows it." -- Alan Perlis
    "Testing can only prove the presence of bugs, not their absence." -- Edsger Dijkstra
    "The only real mistake is the one from which we learn nothing." -- John Powell


    Other boards: DaniWeb, TPS
    Unofficial Wiki FAQ: cpwiki.sf.net

    My website: http://dwks.theprogrammingsite.com/
    Projects: codeform, xuni, atlantis, nort, etc.

  11. #11
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    Quote Originally Posted by dwks View Post
    May I suggest a Makefile template?
    Code:
    # Makefile template
    
    CC = gcc
    CFLAGS = -W -Wall -ansi -pedantic -g
    LDFLAGS =
    
    SOURCES = $(wildcard *.c)
    OBJECTS = $(SOURCES:.c=.o)
    TARGET = executable
    
    # Default target: all
    .PHONY: all
    all: $(TARGET)
    
    # Executable target
    $(TARGET): $(OBJECTS)
    	$(CC) -o $@ $^ $(LDFLAGS)
    
    # Source file dependencies
    
    include depend
    
    .PHONY: depend
    depend:
    	$(CC) -MM $(SOURCES) > depend
    
    # Miscellaneous targets
    .PHONY: clean
    clean:
    	-$(RM) $(OBJECTS) $(SOURCES)
    I have to admit I've never been particularly good with makefiles. I knew it was possible to build the dependencies automatically but I had no idea how. So today, starting a new project, I searched this forum and copied this (more or less, not exactly).

    Then I did a make clean. Are you sure you're supposed to include $(SOURCES) in there? My idea of a clean is not to delete the source files, which in my case it did.

    I feel very lucky I still had another window open with most of the source code (it had only two files). And the other file was about 5 lines .

    So just a warning to everybody who uses it! From the line:
    Code:
    	-$(RM) $(OBJECTS) $(SOURCES)
    REMOVE the $(SOURCES).

  12. #12
    Captain Crash brewbuck's Avatar
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    Quote Originally Posted by EVOEx View Post
    Then I did a make clean. Are you sure you're supposed to include $(SOURCES) in there? My idea of a clean is not to delete the source files, which in my case it did.
    Ouch! Glad you had a "backup." No, $(SOURCES) definitely shouldn't be there. Also, the clean rule doesn't remove $(TARGET) which seems odd.

    (I'm not dwks, author of the buggy makefile )

    I have similar templates for projects using mixed C/C++, and some more complicated examples of build processes that have more steps in them, if you ever want more examples of makefile tricks.

    EDIT: Since I use revision control for everything I work on, I usually don't get too messed up by errors like "blow away your whole tree." At most I lose what I wrote in the last couple of hours.
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

  13. #13
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    Thanks for the responses! I forgot to mention the linux running on the machine is arm linux so I cannot use the full gcc. I have gotten my makefile to find the sources but now I cannot find the .o's. Here is what I have now

    Code:
    all: ks knet_rs232.o knet.o koala.o
    
    # Got to use the right tools
    CC              = arm-linux-gcc
    LD              = arm-linux-ld
    AR              = arm-linux-ar
    AS              = arm-linux-as
    
    KOREBOT_DIR	= /share/robots/libkorebot-1.11/build-korebot/lib/
    KOREBOT_LIB	= korebot-1.11
    KOREBOT_INC	= /share/robots/libkorebot-1.11/build-korebot/include/
    
    export PATH=/share/robots/korebot-tools-2.1/bin:$PATH
    
    #tell make to search this directory and the korebot subdirectory
    VPATH = .:korebot
    
    #
    # Start the rules 
    #
    
    ks: KoalaT.c knet_rs232.o knet.o koala.o
    	$(CC) KoalaT.c knet_rs232.o knet.o koala.o -o KoalaT -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB) -lm
    
    knet_rs232.o: knet_rs232.c knet_rs232.h
    	$(CC) knet_rs232.c -o knet_rs232.o -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    knet.o: knet.c knet.h
    	$(CC) knet.c -o knet.o -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    koala.o: koala.c koala.h
    	$(CC) koala.c -o koala.o -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    
    ########################################################################################
    The output:
    arm-linux-gcc: knet_rs232.o: No such file or directory
    arm-linux-gcc: knet.o: No such file or directory
    arm-linux-gcc: koala.o: No such file or directory

    I know vpath is for the sources, but what do I need to find the .o's? They are in the subdirectory (checked many times).

    Thanks,
    Chris
    Last edited by chris24300; 06-09-2009 at 11:59 AM.

  14. #14
    Captain Crash brewbuck's Avatar
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    You need to specify the object paths explicitly in the targets.

    I never use VPATH. It's too confusing, and doesn't work well (as you discover)
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

  15. #15
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    Right, i tried that but everything I tried didn't seem to work, maybe I screwed up the other vpath stuff I tried. I specified the directory and used the -include option flag and it returned the same thing. Maybe I set it up incorrectly but here it is. I will try your makefile template and see if that will fix my problem.

    Code:
    all: ks knet_rs232.o knet.o koala.o
    
    # Got to use the right tools
    CC              = arm-linux-gcc
    LD              = arm-linux-ld
    AR              = arm-linux-ar
    AS              = arm-linux-as
    
    KOREBOT_DIR	= /share/robots/libkorebot-1.11/build-korebot/lib/
    KOREBOT_LIB	= korebot-1.11
    KOREBOT_INC	= /share/robots/libkorebot-1.11/build-korebot/include/
    KORE = /share/robots/code/ks/korebot
    
    export PATH=/share/robots/korebot-tools-2.1/bin:$PATH
    
    #tell make to search this directory and the korebot subdirectory
    VPATH = .:korebot
    
    #
    # Start the rules 
    #
    
    ks: KoalaT.c knet_rs232.o knet.o koala.o
    	$(CC) KoalaT.c knet_rs232.o knet.o koala.o -o KoalaT -I$(KORE) -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB) -lm
    
    knet_rs232.o: knet_rs232.c knet_rs232.h
    	$(CC) knet_rs232.c -o knet_rs232.o -I$(KORE) -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    knet.o: knet.c knet.h
    	$(CC) knet.c -o knet.o -I$(KORE) -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    
    koala.o: koala.c koala.h
    	$(CC) koala.c -o koala.o -I$(KORE) -I$(KOREBOT_INC) -L$(KOREBOT_DIR) -l$(KOREBOT_LIB)
    Last edited by chris24300; 06-09-2009 at 01:00 PM.

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