Simple GNU Makefile

OriginalCopy · 05-14-2008, 10:48 AM

This is a simple Makefile

Code:

CFLAGS = -Wall
CC = gcc

TESTS := $(wildcard encryption/*.c)

tests: $(TESTS)
    echo "TESTS are compiled under tests/"
    echo "TODO: run the testunit"
#    echo $?
$(TESTS):
    echo $@
#    echo $(CC) $(CFLAGS) -DTEST -o tests/$@ $@.c

The problem is it won't run the commands of the target $(TESTS).

What am I missing?

brewbuck · 05-14-2008, 10:52 AM

Think about what $(TESTS) expands to. For instance, say you have encryption/a.c and encryption/b.c. Then the rule will expand:

encryption/a.c encryption/b.c:
some commands...

There are no dependencies listed. The files exist. Nothing needs to be done, so make does nothing.

OriginalCopy · 05-14-2008, 11:04 AM

Oh I am so dumb. How could I make such that it replaces each .c by "tests/<filename>" and create a target for it automagically, instead of me having to

Code:

encryption/a.c: 
    $(CC) ...

?

brewbuck · 05-14-2008, 11:37 AM

Try something like this:

Code:

CFLAGS = -Wall
CC = gcc

TEST_SRCS = $(wildcard encryption/*.c)
TESTS = $(TEST_SRCS:.c=)

.PHONY: tests

tests:
    $(MAKE) CFLAGS="$(CFLAGS) -DTEST" $(TESTS)

OriginalCopy · 05-14-2008, 12:14 PM

Thanks a lot.

What should I look for in the manual, in regards to $(TEST_SRCS:.c=)?

OriginalCopy · 05-14-2008, 12:17 PM

Never mind, it is in 4.14 Generating Prerequisites Automatically

05-14-2008, 10:48 AM	#1
OriginalCopy Registered User Join Date: May 2008 Posts: 11	Simple GNU Makefile This is a simple Makefile Code: CFLAGS = -Wall CC = gcc TESTS := $(wildcard encryption/*.c) tests: $(TESTS) echo "TESTS are compiled under tests/" echo "TODO: run the testunit" # echo $? $(TESTS): echo $@ # echo $(CC) $(CFLAGS) -DTEST -o tests/$@ $@.c The problem is it won't run the commands of the target $(TESTS). What am I missing?
OriginalCopy is offline

05-14-2008, 10:52 AM	#2
brewbuck Senior software engineer Join Date: Mar 2007 Location: Portland, OR Posts: 5,381	Think about what $(TESTS) expands to. For instance, say you have encryption/a.c and encryption/b.c. Then the rule will expand: encryption/a.c encryption/b.c: some commands... There are no dependencies listed. The files exist. Nothing needs to be done, so make does nothing.
brewbuck is offline

05-14-2008, 11:04 AM	#3
OriginalCopy Registered User Join Date: May 2008 Posts: 11	Oh I am so dumb. How could I make such that it replaces each .c by "tests/<filename>" and create a target for it automagically, instead of me having to Code: encryption/a.c: $(CC) ... ?
OriginalCopy is offline

05-14-2008, 11:37 AM	#4
brewbuck Senior software engineer Join Date: Mar 2007 Location: Portland, OR Posts: 5,381	Try something like this: Code: CFLAGS = -Wall CC = gcc TEST_SRCS = $(wildcard encryption/*.c) TESTS = $(TEST_SRCS:.c=) .PHONY: tests tests: $(MAKE) CFLAGS="$(CFLAGS) -DTEST" $(TESTS)
brewbuck is offline

05-14-2008, 12:14 PM	#5
OriginalCopy Registered User Join Date: May 2008 Posts: 11	Thanks a lot. What should I look for in the manual, in regards to $(TEST_SRCS:.c=)?
OriginalCopy is offline

05-14-2008, 12:17 PM	#6
OriginalCopy Registered User Join Date: May 2008 Posts: 11	Never mind, it is in 4.14 Generating Prerequisites Automatically
OriginalCopy is offline

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