Back to Basics: Direct Memory Access

This is a discussion on Back to Basics: Direct Memory Access within the General Discussions forums, part of the Community Boards category; Hey guys, As programmers one time or another you must have studied the computer and its hardware and software aspects. ...

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    Back to Basics: Direct Memory Access

    Hey guys,
    As programmers one time or another you must have studied the computer and its hardware and software aspects. I have a question about direct memory access and was hoping you guys could guide me through it.

    A 32-bit DLX computer transfers a 512-byte sector (128 words) from the hard disk to the main memory by using DMA. The disk reads the sector from the platter into a special memory called the disk cache which is part of the disk controller. Thereafter the data is transmitted from the disk cache to the main memory via the bus by using DMA. Compute this DMA transfer time from disk cache to main memory. The following are the parameters we know: The bus is 4 words wide and the time to propagate a signal on the bus is 4 processor cycles. (This is often called the bus cycle time.)
    The disk cache is 1 word wide and has an access time of 1 processor cycle.
    The main memory is 16 words wide and has an access time of 80 processor cycles. Assume that main memory accessed cannot be pipelined (i.e., we must wait for the previous access to finish before the next access can be issued.
    The process of transfer is as follows. First, four words are read from the disk cache into hardware registers. When done, they are sent together on the bus in one transfer. When four successive bus transfers are received at the memory, they are written together to the memory. Different stages in this process are overlapped (pipelined) to the extent possible -- carefully think through what can be overlapped.

    My attempt:
    transfer time = (#of words) / (transfer rate)

    # of words = 128
    transfer rate for 16 words = [4 cycles (access disk cache) + 4 cycles (bus transfer)] * 4 (16 words) + 80 cycles ( main memory)

    I sense that this is wrong. Also I don't think any pipeline process is getting over lapped


    Please help out. Newbie here

  2. #2
    Unregistered User Yarin's Avatar
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    What exactly are you asking? You sense what is wrong? Your deduced average transfer rate for a given number of words or sectors?
    A class that doesn't overload all operators just isn't finished yet. -- SmugCeePlusPlusWeenie
    A year spent in artificial intelligence is enough to make one believe in God. -- Alan J. Perlis

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