I'm not really sure what's happening. I think that either the problem is in your makefile, or in your source code. If it's in your makefile, then just compiling the source file by hand should work -- or just get make to print the commands it executes, which it does by default. Or the problem might lie in your source code -- maybe that #if is inside another conditional which is always false or something. I don't know.
Predefine name as a macro, with definition 1.
The contents of definition are tokenized and processed as if they appeared during translation phase three in a `#define' directive. In particular, the definition will be truncated by embedded newline characters.
If you are invoking the preprocessor from a shell or shell-like program you may need to use the shell's quoting syntax to protect characters such as spaces that have a meaning in the shell syntax.
If you wish to define a function-like macro on the command line, write its argument list with surrounding parentheses before the equals sign (if any). Parentheses are meaningful to most shells, so you will need to quote the option. With sh and csh, -D'name(args...)=definition' works.
-D and -U options are processed in the order they are given on the command line. All -imacros file and -include file options are processed after all -D and -U options.