Thread: Help w/Macro and Make

Ok, I've got this macro in main:

Code:

#ifdef LINUXOS

#define PLOT_TYPE_1 "gnuplot gnuplotscript.txt"
#define PLOT_TYPE_2 "gnuplot gnuplotscriptfinal.txt"

#else

#define PLOT_TYPE_1 "wgnuplot.exe gnuplotscript.txt"
#define PLOT_TYPE_2 "wgnuplot.exe gnuplotscriptfinal.txt"

#endif

And my CXX flags in my Makefile are as follows:

Code:

CXXFLAGS := -DLINUXOS -Wall -Wextra -pedantic

But when I compile with the above flags (in Linux obviously) the lines are being replaced with the windows stuff (the lines with wgnuplot.exe).

What am I doing wrong?

Could you post more of your Makefile?

Code:

CXX := g++
CXXFLAGS := -DLINUXOS -Wall -Wextra -pedantic
LDFLAGS :=
SOURCES := $(shell find . -name "*.cpp")
OBJECTS := $(patsubst %.cpp,%.o,$(SOURCES))
DEPENDENCIES := $(patsubst %.cpp,%.d,$(SOURCES))
EXECUTABLE := $(notdir $(shell pwd))

all: $(EXECUTABLE)

$(EXECUTABLE): $(OBJECTS)
	$(CXX) $(LDFLAGS) $(OBJECTS) -o $@
	
-include $(DEPENDENCIES)

%.o: %.cpp
	$(CXX) $(CXXFLAGS) -MMD -MP -MT "$*.d" -c $< -o $@
	
clean:
	rm -rf *.o $(EXECUTABLE)

I'm not sure if it's important, but all the -D's I've seen have an =, as in

Code:

-DLINUXOS=

Ah, never mind that: http://gcc.gnu.org/onlinedocs/gcc/Pr...cessor-Options

-D name
Predefine name as a macro, with definition 1.
-D name=definition
The contents of definition are tokenized and processed as if they appeared during translation phase three in a `#define' directive. In particular, the definition will be truncated by embedded newline characters.

If you are invoking the preprocessor from a shell or shell-like program you may need to use the shell's quoting syntax to protect characters such as spaces that have a meaning in the shell syntax.

If you wish to define a function-like macro on the command line, write its argument list with surrounding parentheses before the equals sign (if any). Parentheses are meaningful to most shells, so you will need to quote the option. With sh and csh, -D'name(args...)=definition' works.

-D and -U options are processed in the order they are given on the command line. All -imacros file and -include file options are processed after all -D and -U options.

I'm not really sure what's happening. I think that either the problem is in your makefile, or in your source code. If it's in your makefile, then just compiling the source file by hand should work -- or just get make to print the commands it executes, which it does by default. Or the problem might lie in your source code -- maybe that #if is inside another conditional which is always false or something. I don't know.

Why don't you try this?

Code:

#ifndef LINUXOS
#error Not linux
#endif

What happens if you try to compile a very simple file with a conditional like that by hand? With your makefile?

errrr, its working now. i was busy with other stuff this whole time, but now it works, and is working good, so yea, i dunno what the deal was, perhaps main.cpp wasn't updated with make or something, yea that's probably it, thanks anyway dwks!

Originally Posted by dudeomanodude

errrr, its working now. i was busy with other stuff this whole time, but now it works, and is working good, so yea, i dunno what the deal was, perhaps main.cpp wasn't updated with make or something, yea that's probably it, thanks anyway dwks!

Yes, I think you may have changed the makefile and not updated main.cpp - it's happened to me more than once!

--
Mats