I was having a problem with a project of mine. I am new to makefiles and I haven't used complicated #include systems, but there appeared a problem with a system of mine:
main.cpp def.h net_funcs.cpp are the files
main.cpp includes def.h
net_funcs.cpp includes def.h
def.h contains some definitions
(main.cpp and net_funcs.cpp both need some of the definitions in the def.h file)
now I have this makefile:
main.exe : main.o net_funcs.o
g++ main.o net_funcs.o -Lc:/cpp/include -lws2_32
main.o : main.cpp
g++ main.cpp -c
net_funcs.o : net_funcs.cpp
g++ net_funcs.cpp -c
when I run make, this will be done:
main.cpp will be compiled (main.o will contain the definitions from def.h)
net_funcs.cpp will be compiled(net_funcs.o will contain the definitions from def.h)
Thus, both files contain the definitions.
when the compiler tries to link them together ( g++ main.o net_funcs.o -Lc:/cpp/include -lws2_32 ) - a clash will occur(double definitions).
So, do you have any ideas of how I should structure my program to make a nice #include system. Is there an universal good style to avoid clashes?