Pipeline freeze simulation
me and my groupmate would like to ask HELP on this one we are required to implement a simulator for a simplified DLX processor, miniDLX. The miniDLX processor offers the following subset of DLX instructions:
1. R-type instructions: ADD, SUB, AND, XOR, SGT
2. I-type instructions: BNEZ, LW, SW, ADDI
3. J-type instruction: J
The miniDLX processor is based on the DLX architecture. Suggested programming language to be used is C.
The objective this project is to “execute” the program using pipeline #2 with the following schemes to solve the hazards:
• Structural Hazard: Separate Memory
• Data Hazard: NO Forwarding (Set B/C/D/E), Forwarding (Set F)
• Control Hazard: Pipeline Freeze
In this case project, we will write the following modules:
1. Utility program to input value for registers R1 to R31
2. Write a simulator program using pipeline #2
A.) Simulation Program
Simulate the program based from the input files: FILENAME.COD; FILENAME.DAT & REGISTER.REG. FILENAME.COD is a file representing the “instruction” memory. It contains the op-code of the program. Each line is sequential in nature (i.e., 1st line is the 1st instruction, 2nd line is the 2nd instruction, etc.) and represents op-code in hex format. The program is always assumed to start at address 0 and succeeding address is incremented by 4. The opcode of the instructions are as follows:
Instruction Opcode Function
ADD 000000 00000000010
SUB 000000 00000000110
AND 000000 00000000000
XOR 000000 00000000001
SGT 000000 00000000111
BNEZ 010000 Not applicable
LW 010001 Not applicable
SW 010010 Not applicable
ADDI 010011 Not applicable
J 100000 Not applicable
FILENAME.DAT is a file representing the “data” memory. Each line is sequential in nature (i.e., 1st line is the 1st word data, 2nd line is the 2nd word data.) and in hex format. The data is always assumed to start at address 0 and the succeeding address is incremented by 4.
Simulate the instructions by showing the contents of the registers/memory that will be affected in each clock cycle (i.e., like the examples shown above) Thus:
Cycle 1: IF/ID.IR, IF/ID.NPC, PC;
Cycle 2:ID/EX.A, ID/EX.B, ID/EX. IMM, ID/EX.IR;
Cycle 3:EX/MEM.ALUOUTPUT, EX/MEM.ALUOUTPUT, EX/MEM.B (for LW & SW)
Cycle 4:MEM/WB.IR, MEM/WB.ALUOUTPUT ( for ALU), MEM/WB.LMD (for LW), MEM[ALUOUTPUT] (for SW)
Cycle 5: Register affected
Note: Obviously, the simulation assumes separate memory for data and program. PC starts at zero.
Note: There is no “COND” register in pipeline #2. Please refer to the appropriate algorithm for Pipeline #2
Note: The affected registers/memory should contain the actual value.
Note: FILENAM.DAT and FILENAME.COD is provided by the professor.
Note: You have the option of having text-based or graphics-based output. The most important part is the correctness of value.
we dont know were to start, please give us clear coding on this to starto to..thanks