Make files

This is a discussion on Make files within the C Programming forums, part of the General Programming Boards category; Hi, I am trying to build a make file then when we type make it cleans up all the object ...

  1. #1
    Registered User
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    Feb 2006
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    Make files

    Hi,

    I am trying to build a make file then when we type make it cleans up all the object files and the .exe file and compile everytime even though I didnot modify anything. But mine doesnot work.

    Code:
    .
    PHONY :clean
    
     CC = gcc
    test: test.o
    	gcc test.o -o test
    	
    test.o:test.c
    	gcc -c test.c 
    
    	clean:
    	rm test.exe test.o

  2. #2
    int x = *((int *) NULL); Cactus_Hugger's Avatar
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    1.) Make sure there is no whitespace before CC = gcc and clean:.
    2.) I think it's .PHONY : clean

    Also, you'll need to type make clean (or make -f makefile_name clean if your makefile isn't named "Makefile") Note that makefile clean will only clean, not compile... usually you do:
    Code:
    $ make clean
    $ make
    If you're wanting to clean every time, perhaps a short script? Otherwise, I wouldn't know how, or why, since cleaning all the dependants each time sort of defeats the purpose of a makefile... it becomes a mindless batch file.

    Here's my hopefully correct version:
    Code:
    CC = gcc
    
    .PHONY : clean all
    all : test
    
    test: test.o
    	gcc test.o -o test
    	
    test.o: test.c
    	gcc -c test.c 
    
    clean:
    	rm test.exe test.o
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  3. #3
    Frequently Quite Prolix dwks's Avatar
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    There's a default rule that compiles .c files into .o files, so you don't need this:
    Code:
    test.o: test.c
    	gcc -c test.c
    dwk

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