I'm assuming they mean each disk access and memory access is a 32-bit fetch. But w/o more info I cannot answer your second question.
The two level page table is fairly simple. It simply means there are two page tables - but again I'm not familiar with your implementation so anything is possible. Since they are using 9 bits to represent the table offset I'm assuming that each table is only 2^9 bytes in size which gives 2*(2^9) or 512*2 or 1024 bytes. However each ENTRY in the page table...each address stored in the page table is 32-bits.
The page table entry size has little or nothing to do with the virtual address contents. So this means that since each page table is 512 bytes in size and each address entry is 4 bytes that the max amount of entries is (512/4) or 128.
You can store 128 entries in each page table for a max of 256 entries.
Page table 1: - 32 bit entries, 128 - 32-bit entries allowed
Entry 0 0xFFFFFFFF
Entry 1 0x1234567
Entry 2 .................
Entry 127 0x00000000