Divide by 3 in ISR

This is a discussion on Divide by 3 in ISR within the C Programming forums, part of the General Programming Boards category; It is not home work. It is ISR in embedded system and this ISR is invoked when hardware timer expires....

  1. #31
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    It is not home work. It is ISR in embedded system and this ISR is invoked when hardware timer expires.

  2. #32
    Registered User Codeplug's Avatar
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    Who is the provider of your kernel?
    What type of timer and on what CPU?

    gg

  3. #33
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    There is no kernel or OS, image directly runs on x186 processor. This has 16 bit timer. With our current clock frequency of 15.67 MHz we can generate a delay of 133.3 ms. If I want more than this delay we loop it. So I need to check remaing time in ISR load the timer with remaining value and kicks the timer again.

    So I need to mulitply the a value by frequency value.

    e.g
    x * 15.67 = ( x * 16 ) - ( x - 1/3) = ( x << 4) - ( x * 1/3).

    Now I want to get rid of last division also.

  4. #34
    Just Lurking Dave_Sinkula's Avatar
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    Quote Originally Posted by Roaring_Tiger
    x * 15.67 = ( x * 16 ) - ( x - 1/3) = ( x << 4) - ( x * 1/3).

    Now I want to get rid of last division also.
    Why not this?
    Code:
    y = (x * 47) / 3; /* 47 / 3 = 15.67 */
    (I'm still wondering why you are avoiding / and *.)
    Last edited by Dave_Sinkula; 08-20-2004 at 04:32 PM.
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  5. #35
    Registered User Codeplug's Avatar
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    >> y = (x * 47) / 3;
    That's as fast as it gets with accuracy.

    You can get a tad bit more accuracy using fixed-point math and rounding (but not as fast as above):
    [edit]and more prone to overflow[/edit]
    >>y = ((((x * 100) * 1567) + 5000) / 10000);

    gg
    Last edited by Codeplug; 08-20-2004 at 04:51 PM.

  6. #36
    & the hat of GPL slaying Thantos's Avatar
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    why not just use:
    y = x * 15.67
    15.67 is a constant
    Unless of course your chip can't do floating point multiplication nativily

  7. #37
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    There is no floating point unit in the processor. Forget that, there in no much memory( only 6K ) and code needs to execute very fast. This processor takes 3 bytes for divide and multiply. And approximately 48 clock cycles for division and multiplication, which is approximately 3 micro seconds. Sub and Add takes 24. Shifts only 12 clock cycles. We need accurancy in microseconds. And that is the reason, I am trying to cutdown on * and /.

  8. #38
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    I'd say you're looking at some assembly then.

    Besides:
    ( x << 4) - ( x * 1/3)
    shift + sub + (shift ideally) = 12+24+12 = 48

    And:
    x * 15.67
    mul = 48

    So the suggestion already meets your ideal clock cycle count. Unless I missed something (which I probably did).
    Last edited by itsme86; 08-20-2004 at 10:37 PM.
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  9. #39
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    itsme86: Please explain your solution..

    RT

  10. #40
    and the hat of wrongness Salem's Avatar
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    > This has 16 bit timer. With our current clock frequency of 15.67 MHz we can generate a delay of 133.3 ms
    I can't figure out what the relationship is between your clock speed, the maximum delay and your 16 bit counter.

    But instead of loading your counter with 0xFFFF to get a delay of 133.333ms, try loading it with 0xC000 and get a delay of 100ms.

    Or some ofher odd value in the counter which makes for much easier maths inside your ISR.
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  11. #41
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    >I can't figure out what the relationship is between your clock speed, the maximum delay >and your 16 bit counter.

    Why not???

    >But instead of loading your counter with 0xFFFF to get a delay of 133.333ms, try loading it >with 0xC000 and get a delay of 100ms.

    That's what we decided to do. Delay for 128 ms.

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