Thread: Aligning Code

I am a bit unsure about what this piece of code aligning a struct to a page is trying to achieve.

Code:

#define PAGESIZE 1 << 12

 typedef struct __attribute__((aligned(PAGESIZE))) x86_pagetable {
     x86_pageentry_t entry[PAGETABLE_NENTRIES];
 } x86_pagetable;

It is an piece of code from an educational operating system WeenyOS.

What is the essence of aligning a struct to a page?

Originally Posted by Salem

operating system - How do x86 page tables work? - Stack Overflow
Because the CR3 register only has 20 bits to point to the page table, so the CPU assumes the lower 12 bits must be zeros.
Hence the page table has to be on a 4K boundary.

Aah, thanks.

Originally Posted by Salem

operating system - How do x86 page tables work? - Stack Overflow
Because the CR3 register only has 20 bits to point to the page table, so the CPU assumes the lower 12 bits must be zeros.
Hence the page table has to be on a 4K boundary.

Do you rather mean that the last 12 bits set the access mode?

Originally Posted by Aslaville

Do you rather mean that the last 12 bits set the access mode?

Arrg Am a bit confused

Originally Posted by Aslaville

Do you rather mean that the last 12 bits set the access mode?

Well, you must have.

What you guys are you talking about even. It appears that the site needs to provide some form of speech therapist services or smth

Page table entry format is irrelevant here. What is relevant, is that the x86 family processors need to know the address of the page table. The CR3 register defines the location of the page table, and like Salem said,

Originally Posted by Salem

Because the CR3 register only has 20 bits to point to the page table, so the CPU assumes the lower 12 bits must be zeros.
Hence the page table has to be on a 4K boundary.

Or, put another way, the address of the page table must be a multiple of 2¹² = 4096.

As the GCC online documentation on type attributes describes, the __attribute__ ((aligned (ALIGNMENT))) attribute aligns all variables of that type to a multiple of ALIGNMENT (if possible).

TL;DR:

The code defines a type, x86_pagetable, that the compiler should try its best to make sure is always aligned to 4096 bytes.

The type is a structure type with one member, entry. It is an array of PAGETABLE_NENTRIES elements of type x86_pageentry_t.

Originally Posted by Nominal Animal

Page table entry format is irrelevant here. What is relevant, is that the x86 family processors need to know the address of the page table. The CR3 register defines the location of the page table, and like Salem said,

Or, put another way, the address of the page table must be a multiple of 2¹² = 4096.

As the GCC online documentation on type attributes describes, the __attribute__ ((aligned (ALIGNMENT))) attribute aligns all variables of that type to a multiple of ALIGNMENT (if possible).

TL;DR:

The code defines a type, x86_pagetable, that the compiler should try its best to make sure is always aligned to 4096 bytes.

The type is a structure type with one member, entry. It is an array of PAGETABLE_NENTRIES elements of type x86_pageentry_t.

I keep going over it again and start getting confused.

Thanks!

Originally Posted by Salem

So aside from "__attribute__((aligned(PAGESIZE)))", do you know what it says?

Because if you don't, I don't see how you're ready for where this is going.

I didn't quite get your question,,, but I think you are asking the structure of the pagetable.

It should be something like:

- the first entry is the page directory entry which you can get from a virtual address by

Code:

#define L1PAGEINDEX( (uintptr_t) va >> 22)

- I use the l1 page index to index the pagetable and get the pagetable entry.

Code:

/* for instance to check the access rights */
       #define PTE_U        ((x86_pageentry_t) 4)

      kernel_pagetable[L1PAGEINDEX(va)] & PTE_U;

Well, I guess this should be done by 'anding' the bits from the 'page directory' entry and those from the 'page table entry'.

And of course I am missing a lot of other stuff.

I have no idea I am not rambling.