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Variables in Makefile

This is a discussion on Variables in Makefile within the C Programming forums, part of the General Programming Boards category; I'm sure this isn't the best way to do it, and tools like autoconf and cmake would be better, but ...

  1. #1
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    Variables in Makefile

    I'm sure this isn't the best way to do it, and tools like autoconf and cmake would be better, but I really just want something quick and dirty.

    Basically, I have code in a distributed system that's supposed to run on a number of different machines with different hardware. I just want to do something simple by having some targets that set variable values, and then calls a general make that uses those variables.

    On each machine, I have to link to a library that's compiled specifically for that machine (it exposes the same interface, so i don't need to change my code).

    For example

    Code:
    titan:
           PATH_TO_INCLUDE=/path/to/include/on/titan
           PATH_TO_LIBRARY=/path/to/library/on/titan
           etc. ect. 
           make common
    cielo:
           PATH_TO_INCLUDE=/path/to/include/on/cielo
           PATH_TO_LIBRARY=/path/to/library/on/cielo
           make common
    
    common
          gcc -c something.c -I $(PATH_TO_INCLUDE)
          gcc -o something.o -L $(PATH_TO_LIBARY)

    however, it seems that the PATH_TO_* variables aren't kept across target invocations.

    What am I missing here, or am I just completely off base?

    Thanks.

  2. #2
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    You probably need to export the variable PATH_TO_INCLUDE in order for the subshells to see it. Also, when calling make recursively, the proper way is

    Code:
    $(MAKE) ...
    Recursion - GNU `make'

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    Quote Originally Posted by c99tutorial View Post
    You probably need to export the variable PATH_TO_INCLUDE in order for the subshells to see it. Also, when calling make recursively, the proper way is

    Code:
    $(MAKE) ...
    Recursion - GNU `make'
    Export.. interesting. Is there a way to make different targets from within the same make instance?

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    Quote Originally Posted by gzhispanic View Post
    Is there a way to make different targets from within the same make instance?
    It looks like that's what you're doing in your original sample. Each target is a label starting in the first column and ending with a colon.

    The idea of the recursive make is that you have some subprojects in separate directories, each with its own Makefile. Rather than always adding in new projects into your Makefile (which makes it longer and harder to maintain), you can break it up into small simpler Makefiles. Then your main cd into each subproject and run make recursively.

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