A Makefile is just a text file that contains definitions and rules for building your programs. It's like source code for a special scripting language. They look a bit scary at first, but they're not too bad. Here's the makefile from your project:
Code:
# based on http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/
# Sat Apr 14 11:01:20 CDT 2012
CC=gcc
SRC=hw10-brezeale.c
BINLIB=binary-lib.c
DEPS=binary-lib.h
# type
# make
# to build
a.out: ${SRC} ${BINLIB} ${DEPS}
${CC} -std=c89 -pedantic ${SRC} ${BINLIB}
# type
# make clean
# to remove a.out
clean:
rm a.out
The lines that start with # are comments. A comment can start anywhere, on any line, and everything from the # to the end of the line is ignored, like a // comment in C/C++/Java (though your prof looks to make you use pedantic C89 rules for C, which doesn't support that style comment).
- Those things are variables. Simply put, wherever you use $(VARIABLE) later on, it gets replaced by whatever is on the right side of the = sign.
- Those things are called targets. They are the different things you can make. You can type "make a.out", or "make clean" from the command line. clean is a conventional name that gets rid of stuff created by the build process itself (i.e. it leaves your source code, but removes executables, temporary files, etc). If you type "make" without specifying a target, it uses the first one in the file, so "make" would be equivalent to "make a.out" in this case.
- Those things are the commands to run when making the target. a.out runs $(CC) -std=c89 -pedantic $(SRC) $(BINLIB), which gets translated (by substituting the variable's values) to gcc -std=c89 -pedantic hw10-brezeale.c binary-lib.c as though you typed it from the command line yourself.
- Those things are called dependencies. They are what are required when you make a target. Thus, a.out requires $(SRC), $(BINLIB) and $(DEPS). By "requires", it really checks when the file was modified. That is, any of the dependencies have a more recent timestamp than the target, Make will re-run the commands for the target, to bring the target "up to date" with your latest version of the source code. That is, if you do "make a.out", then go change something in binary-lib.c, and retype "make a.out", make will look at the dependencies for a.out. It will see that the binary-lib.c file is more recent than the a.out file, and re-run all the commands for that target. If you don't change binary-lib, make will tell you something like "target 'a.out' is up to date". Notice that clean has no dependencies. That means it always performs the commands, no matter what.
The whole combination of target, dependencies and commands form a rule in Make terminology.
Note, I used parentheses for the variables instead of curly braces because the forum software only lets you put curly braces inside code tags. However, Make allows you to use either form, and (AFAIK) they both behave the same way.
Make is much more powerful and complex than just what you see, and what I explained. Where I used words like "always", "never", etc, there are most likely exceptions to many/all of those "absolutes", but they're not relevant here and will probably just confuse you right now, so I left them out.
Now for the good part: it looks like all you have to do is change the definition of SRC, to match whatever files you use, i.e. hw10-LastnameFirstname.c for your last and first name.
