makefiles on windows

[Galapp]

Hi,

I am taking a C/C++ course and we're required to make makefiles to run our code... however I just don't understand how to create them. I downloaded GnuWin32, I understand that this is what the file should contain:

all: proj1


proj1: proj1.o


proj1.o: proj1.c
	gcc proj1.c -o proj1

thinking that the output file is proj1.o and the only source file is proj1.c... now the few questions I have are:

how do I create this file? notepad? cmd?
if I have .h files involved but they're system files they arent part of my project, do I still need them? I have this in my code:
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h> /* for fork */
#include <sys/types.h> /* for pid_t */
#include <sys/wait.h> /* for wait */

this is for an Operating Systems Concept class and the assignment is to work with fork() processes... all I need is to figure out how on earth I make a makefile.

thanks and I apologize for the "n00b" question.

[anduril462]

Why try an make Windows act like a *nix system? Why not just download free VM software like VirtualBox and install a Linux system? You can develop on that directly, it will probably be much closer to your school environment, so there will be less problems as you move your code from your home development setup to school. It has native support for things like fork() and wait(), and makefiles, no need to mess around with GnuWin32

Makefiles are just plain text files. Editing them in notepad would work, but I prefer a bit of syntax highlighting, so something a bit fancier, like notepad++ would be good. But do be careful, makefiles are very picky about using actual tabs, not "spaces as tabs", as many people have their editors set up. In your case, you don't really need to include system headers as dependencies for any of your targets, since the system headers probably rarely or never change, at least not mid-semester, so you wont need to worry about rebuilding your project because the system headers changed.

The makefile you posted could use a bit of work. Try this out, and study it. It should allow you to use the same make file for each project with minimal changes. Just change TARGET to proj2 or whatever, and change any .c files you need if you're not using the wildcard trick.

EXE=proj1
# list any other .c files you need, or use $(wildcard *.c) to get all .c files in the current directory
SRCS=proj1.c
# convert each .c file in SRCS into it's .o counterpart, and store them in OBJS
OBJS=$(SRCS:%.c=%.o)

all: $(EXE)

$(EXE): OBJS # add any other .o files you need
    # $@ is the target (what's left of the colon, proj1 in this case).  @^ is all the prereqs, i.e. all the .o files in OBJS
    gcc -Wall -o $@ $^

# The % is a wild card, so foo.o depends on foo.c, bar.o on bar.c, etc.  It's a generic rule for making any .o file from it's corresponding .c
%.o: %.c
    # -c compiles only to a .o file, $@ is the target (.o file) and $< is the first dependency (.c file)
    gcc -Wall -c -o $@ $<