Help me understand GNU Make please

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  1. #1
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    Help me understand GNU Make please

    What is the implicit rule for handling a header file as a prerequisite?

    e.g
    Code:
         main.o : defs.h
         kbd.o : defs.h command.h
         command.o : defs.h command.h
         display.o : defs.h buffer.h
         insert.o : defs.h buffer.h
         search.o : defs.h buffer.h
         files.o : defs.h buffer.h command.h
         utils.o : defs.h
    Does Make automatically know to compile defs.c for example?

  2. #2
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    As defs.c is not listed as a target dependency in this case so it won't know, unless there is more to this makefile.

  3. #3
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    I got this code from the Make manual.
    make Deduces - GNU `make'

    Code:
         objects = main.o kbd.o command.o display.o \
                   insert.o search.o files.o utils.o
         
         edit : $(objects)
                 cc -o edit $(objects)
         
         main.o : defs.h
         kbd.o : defs.h command.h
         command.o : defs.h command.h
         display.o : defs.h buffer.h
         insert.o : defs.h buffer.h
         search.o : defs.h buffer.h
         files.o : defs.h buffer.h command.h
         utils.o : defs.h
         
         .PHONY : clean
         clean :
                 rm edit $(objects)

  4. #4
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    Quote Originally Posted by yougene View Post
    What is the implicit rule for handling a header file as a prerequisite?
    There is no such implicit rule. Is this an example from a real makefile, or an example you made up for the purposes of this question?

    If the rule:

    Code:
    main.o: defs.h
    actually causes make to compile main.c into main.o (I don't know, I haven't tried), then it means that make is MERGING the explicit rule with the implicit rule. It is the implicit rule which tells make to compile a .c source file. The explicit rule is just adding a dependency to the list of dependencies for that target.

    But I'm not sure if make actually operates that way (merging rules), which is why I ask if this is a functional example or not.
    Code:
    //try
    //{
    	if (a) do { f( b); } while(1);
    	else   do { f(!b); } while(1);
    //}

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    The make utility has built-in rules on how to create the target, edit in this case based on the provided object files (*.o). There's no defs.c only a defs.h, which is a header file that all the object modules depend upon. Each object file has a corresponding source file with the same prefix and a .c extension. So for example object file main.o will have a corresponding main.c source file and using the built-in information make knows to create main.o, as in:
    Code:
    cc -c main.c

  6. #6
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    Quote Originally Posted by brewbuck View Post
    There is no such implicit rule. Is this an example from a real makefile, or an example you made up for the purposes of this question?
    This is an example from the Make manual so I think it is supposed to be a working example.


    I just realized that all the targets are object files which means no linking will be done. That makes alot more sense to me.

    Thanks for the input guys

  7. #7
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    Quote Originally Posted by yougene View Post
    I just realized that all the targets are object files which means no linking will be done. That makes alot more sense to me.
    With the exception of the target edit, which is a full-blown executable as it has passed through ld (the link-editor).

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